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AD8152

34 ⴛ 34, 3.2 Gbps

Asynchronous Digital Crosspoint Switch

REV. A

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FEATURES

Low Cost

Low Power

2.0 W @ 2.5 V (Outputs Enabled)

<100 mW @ 2.5 V (Outputs Disabled)

34 ⴛ 34, Fully Differential, Nonblocking Array

3.2 Gbps per Port NRZ Data Rate

Wide Power Supply Range: 2.5 V to 3.3 V

LVTTL or LVCMOS Level Control Inputs:

@ 2.5 V to 3.3 V

Low Jitter: 45 ps

Drives a Backplane Directly

Programmable Output Swing

100 mV to 1.6 V Differential

50 ⍀ On-Chip I/O Termination

User Controlled Voltage at the Load

Minimizes Power Dissipation

Dual Rank Latches

Available in 256-Ball Grid Array

APPLICATIONS

Fiber Optic Network Switching

High Speed Serial Backplane Routing to OC-48 with FEC

Gigabit Ethernet

Digital Video (HDTV)

Data Storage Networks

FUNCTIONAL BLOCK DIAGRAM

OUTPUT

LEVEL

DACs

OUTN

OUTP

VTTO

34 ⴛ 34

DIFFERENTIAL

SWITCH MATRIX

MATRIX

CONNECTION

LATCHES

CONNECTION

DECODE

OUTPUT

LEVEL

LATCHES

CONTROL

LOGIC

INN

VTTI

INP

D[5:0]

A[6:0]

RESET

UPDATE

VEE

VCC

AD8152

GENERAL DESCRIPTION

AD8152 is a member of the Xstream line of products and is a

breakthrough in digital switching, offering a large switch array

(34 × 34) on very little power, typically 2.0 W. Additionally, it

operates at data rates up to 3.2 Gbps per port, making it suitable

for Sonet/SDH OC-48 with Forward Error Correction (FEC).

The AD8152’s useful supply voltage range allows the user to

operate at LVPECL/CML data levels down to 2.5 V. The control

interface is LVTTL or LVCMOS compatible on 2.5 V to 3.3 V.

The AD8152’s fully differential signal path reduces jitter and

crosstalk while allowing the use of smaller single-ended voltage

swings. It is offered in a 256-ball SBGA package that operates

over the industrial temperature range of 0°C to 85°C.

80ps/DIV

100mV/DIV

Figure 1. Eye Pattern, 3.2 Gbps, PRBS 23

Summary of content (32 pages)

PAGE 1
a 34 ⴛ 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch AD8152 FEATURES Low Cost Low Power 2.0 W @ 2.5 V (Outputs Enabled) <100 mW @ 2.5 V (Outputs Disabled) 34 ⴛ 34, Fully Differential, Nonblocking Array 3.2 Gbps per Port NRZ Data Rate Wide Power Supply Range: 2.5 V to 3.3 V LVTTL or LVCMOS Level Control Inputs: @ 2.5 V to 3.3 V Low Jitter: 45 ps Drives a Backplane Directly Programmable Output Swing 100 mV to 1.
PAGE 2
AD8152 (@ 25ⴗC, VCC = 2.5 V to 3.3 V, VEE = 0 V, RL = 50 ⍀, Differential Output Swing = 800 mV p-p, ELECTRICAL CHARACTERISTICS unless otherwise noted.
PAGE 3
AD8152 ABSOLUTE MAXIMUM RATINGS 1 16 Tj = 150ⴗC MAXIMUM POWER DISSIPATION – W VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 V VTTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V VTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V Internal Power Dissipation2 AD8152 256-Ball SBGA (BP) . . . . . . . . . . . . . . . . . . 8.33 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.
PAGE 4
AD8152 BALL GRID ARRAY 20 19 18 17 16 A VEE VEE VEE VEE VCC B VEE VEE VEE VEE C VEE VEE D4 D D0 D1 E CS F 15 14 13 12 9 8 7 6 5 4 3 2 1 VTTO O14P VTTO O11P VCC O08P VTTO O05P VTTO O02P VTTO VCC VEE VEE VEE A VCC VTTO O14N VTTO O11N VCC O08N VTTO O05N VTTO O02N VTTO VCC VEE VEE VEE B D5 O16N O15P O13N O12P O10N O09P O07N O06P O04N O03P O01N O00P A6 A5 VEE VEE C D2 D3 O16P O15N O13P O12N O10P O09N O07P O06N O04
PAGE 5
AD8152 BALL GRID DESCRIPTIONS Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Mnemonic VEE VEE VEE VCC VTTO OUT02P VTTO OUT05P VTTO OUT08P VCC OUT11P VTTO OUT14P VTTO VCC VEE VEE VEE VEE VEE VEE VEE VCC VTTO OUT02N VTTO OUT05N VTTO OUT08N VCC OUT11N VTTO OUT14N VTTO VCC VEE VEE VEE VEE VEE VEE A5 A6 OUT00P OUT01N OUT03P OUT04N OUT06P OUT07N OUT09P REV.
PAGE 6
AD8152 BALL GRID DESCRIPTIONS (continued) Ball G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 Mnemonic IN19N IN19P VTTI VTTI IN03P IN03N IN20N IN20P VTTI VTTI IN05P IN05N IN04N IN04P IN21P IN21N IN22N IN22P VTTI VTTI IN06P IN06N IN23N IN23P VTTI VTTI IN08P IN08N IN07N IN07P IN24P IN24N IN25N IN25P VCC VCC IN09P IN09N IN26N IN26P VCC VCC IN11P IN11N IN10N IN10P IN27P IN27N IN2
PAGE 7
AD8152 BALL GRID DESCRIPTIONS (continued) Ball V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Mnemonic OUT23P OUT24N OUT26P OUT27N OUT29P OUT30N OUT32P OUT33N VEE VEE VEE VEE VEE VEE VEE VCC VTTO OUT19N VTTO OUT22N VTTO OUT25N VCC OUT28N VTTO OUT31N REV.
PAGE 8
AD8152–Typical Performance Characteristics (2.5 V Supply, VCC = VTTI = VTTO, Data Rate = 3.2 Gbps; 100mV/DIV 100mV/DIV PRBS 223–1; Differential Output Swing = 800 mV p-p; RL = 50 ⍀; Input Amplitude = 0.4 V p-p Single-Ended; unless otherwise noted.) 80ps/DIV 200ps/DIV TPC 4. Eye Pattern 1.5 Gbps 100mV/DIV 100mV/DIV TPC 1. Eye Pattern 3.2 Gbps PEAK-PEAK JITTER = 35ps STD DEV = 5.1ps PEAK-PEAK JITTER = 35ps STD DEV = 5.2ps 20ps/DIV 20ps/DIV TPC 5. Jitter @ 1.5 Gbps 100mV/DIV 100mV/DIV TPC 2.
PAGE 9
AD8152 1.E+00 1400 BIN WIDTH = 5ps 1.E–01 1200 1.E–02 1.E–03 BIT ERROR RATE FREQUENCY 1000 800 600 400 1.E–04 1.E–05 1.E–06 1.E–07 1.E–08 1.E–09 1.E–10 200 1.E–11 0 –50 –40 –30 –20 –10 0 10 20 40 30 1.E–12 –0.5 50 DUTY CYCLE DISTORTION – ps TPC 7. Duty Cycle Distortion Distribution –0.4 –0.3 –0.2 –0.1 0 0.1 UNIT INTERVAL 0.2 0.3 0.4 0.5 TPC 10. Bit Error Rate vs. Unit Interval 100 90 80 60 %EYE HEIGHT = VOUT @ DATA RATE ⴛ100 VOUT @ 0.
PAGE 10
AD8152 55 80 70 50 PEAK-PEAK JITTER – ps 60 45 JITTER – ps 1.5 Gbps 40 3.2 Gbps 35 50 PEAK-PEAK JITTER 40 30 20 STANDARD DEVIATION 30 10 25 0 10 20 30 40 50 60 70 80 0 1.8 2.0 90 2.2 2.4 TEMPERATURE – ⴗC 2.8 3.0 3.2 3.4 3.6 3.8 4.0 TPC 16. Jitter vs. Supply TPC 13. Single Point Jitter vs. Temperature 120 160 140 PEAK-PEAK JITTER – ps 100 80 JITTER – ps 2.
PAGE 11
AD8152 750 160 BIN WIDTH = 5ps 140 PROPAGATION DELAY – ps 725 FREQUENCY 120 100 80 60 40 700 675 650 625 20 0 600 625 650 675 700 PROPAGATION DELAY – ps 725 600 2.0 750 800 780 740 720 IOUT – mA PROPAGATION DELAY – ps 760 700 680 660 640 620 0 10 20 30 40 50 60 TEMPERATURE – ⴗC 70 80 90 TPC 20. Propagation Delay vs. Temperature REV. A 2.4 2.6 2.8 3.0 3.2 SUPPLY VOLTAGE – V 3.4 3.6 3.8 TPC 21. Propagation Delay vs. Supply TPC 19. Variation in Propagation Delay 600 2.
PAGE 12
AD8152 VCC VTTI PATTERN GENERATOR DATA OUT VTTO IN##P –6dB HIGH SPEED SAMPLING OSCILLOSCOPE –6dB OUT##P 50⍀ AD8152 DATA OUT IN##N –6dB –6dB OUT##N 50⍀ TRIGGER OUT VEE = –2.5V TRIGGER IN IOUT = 16mA, VOUT HI = 0V, V OUT LO = –0.4V VIN AMPLITUDE = 400mV p-p SINGLE-ENDED, VIN HI = –0.2V PRBS 223 – 1 TPC 23. Negative Supply Test Circuit 2.5V DATA OUT VCC VTTI PATTERN GENERATOR 0.1␮F OUT##P IN##P –6dB HIGH SPEED SAMPLING OSCILLOSCOPE VTTO 0.
PAGE 13
AD8152 Table I. Address and Data Buses Connection/Current Bit Output Address Pins A6 0 = CONNECTION LATCHES 1 = OUTPUT CURRENT LEVEL A5 A4 A3 Data Pins A2 A1 MSB A0 D5 LSB MSB D4 D3 D2 D1 D0 LSB Table II.
PAGE 14
AD8152 CS WE A[6:0]INPUTS D[5:0]INPUTS tCSW tAHW CHW tASW tAHW tWP tDSW tDHW Figure 3a. First Rank Write Cycle Table V. First Rank Write Cycle Symbol Parameter Conditions Min Chip Select to Write Enable Address to Write Enable Data to Write Enable TA = 25ⴗC 0 0 1 ns ns ns 0 0 0 ns ns ns 10 ns tCSW tASW tDSW Setup Time tCHW tAHW tDHW Hold Time tWP Width of Write Enable Pulse VCC = 3.
PAGE 15
AD8152 CS UPDATE WE ENABLING OUT[0:33][N:P] OUTPUTS DISABLING OUT[0:33][N:P] OUTPUTS INPUT {DATA 1} INPUT {DATA 0} tCSU INPUT {DATA 2} INPUT {DATA 1} tCHU tUW tWOT tUOT tUOE tWHU tWOD Figure 4a. Transparent Write and Update Cycle Table VII. Transparent Update Cycle Symbol Parameter Conditions Min TA = 25ⴗC VCC = 3.
PAGE 16
AD8152 RESET DISABLING OUT[0:33][N:P] OUTPUTS tTOD tTW Figure 5. Asynchronous Reset Table IX. Asynchronous Reset Symbol tTOD Disable Time tTW Width of Reset Pulse Parameter Conditions Output Disable from Reset TA = 25ⴗC VCC = 3.3 V CONTROL INTERFACE The AD8152 control interface receives and stores the desired connection matrix and output levels for the 34 input and 34 output signal pairs. The interface consists of 34 rows of double-rank 6-bit latches, one for each output.
PAGE 17
AD8152 CS Input Chip select. This pin must be forced to logic low to program or receive data from the logic interface, with the exception of the RESET pin, described below. This pin has no effect on the signal pairs and does not alter any of the stored control data. RESET Input Global output disable pin. Forcing the RESET pin to logic low will disable all outputs, setting both ranks of all 34 input connection latches, regardless of the state of any other pins.
PAGE 18
AD8152 Input Coupling One way to simplify the input circuit and make it compatible with a wide variety of driving devices is to use ac coupling. This has the effect of isolating the dc common-mode levels of the driver and the AD8152 input circuitry. For example, the XAUI interconnect specification for 10 Gbps Ethernet requires ac coupling in order to ensure that there are no interactions of dc levels between the transmitting and receiving devices.
PAGE 19
AD8152 is powered down. Thus, the total number of active inputs will affect the total power consumption. AD8152 POWER CONSUMPTION There are several sections of the AD8152 that draw varying power depending on the supply voltages, the type of I/O coupling used, and the status of the AD8152 operation. Figure 9 shows a block diagram of these sections. These are described briefly below and then in detail later in the data sheet.
PAGE 20
AD8152 of these two currents will flow through the switches and the current source of the AD8152 output circuit and out through VEE. The power dissipated in the transmission line and the destination resistor will not be dissipated in the AD8152, but will have to be supplied from the power supply, and is a factor in the overall system power. The current in the on-chip termination resistors and the output current source will dissipate power in the AD8152 itself.
PAGE 21
AD8152 First, the output current can be programmed to the smallest amount required to maintain BER performance. If an output circuit always has a short length and the receiver has good sensitivity, then a lower output current can be used. ALL TOP-MOUNT SMAs SIT ON PCB TOP LEVEL SMA CENTER PIN MICROSTRIP It is also possible to lower the voltage on VTTO to lower the power dissipation. The amount that VTTO can be lowered is dependent on the lowest of all the output’s VOL.
PAGE 22
AD8152 Figure 12. Cross-Sectional Layout and Dimensioning (To Scale) of Differential The variety of supply configurations cause the need for a supply agile digital control circuitry. This is done by a programmable logic device (PLD), which provides instructions to the AD8152. The PLD supply is typically tied with jumpers across the AD8152’s VCC and VEE supplies (Jumpers J3 and J4). The PLD is addressed from the PC by way of digital isolators.
PAGE 23
AD8152 This would require VTTI to be attached to ground, causing excessive power to be dissipated in the internal 50 W input termination resistors. Secondly, when the AD8152 output tries to drive its own input with VTTI = 0 V and VTTO = 2.5 V, the input will pull the output stage levels down enough to shut off any signal toggling. VCC VTTO AD8152 P ECL DRIVER All ac coupling shown is actually done with a set of bias tees.
PAGE 24
AD8152 Next, select the desired output from the Output Select box by doubleclicking the appropriate output channel number. EVALUATION BOARD CONTROL SOFTWARE The AD8152 evaluation board can be controlled by using a PC and a custom software program. The hardware interface uses a PC parallel (or printer) port. A standard printer cable is used to connect from the PC DB-25 connector to the Centronics-type connector on the evaluation board. Figure 17 shows an evaluation board control panel from a PC display.
PAGE 25
AD8152 Figure 18. Evaluation Board Top Side Signals REV.
PAGE 26
AD8152 Figure 19. Evaluation Board Bottom Side Signals, View from Top –26– REV.
PAGE 27
AD8152 Figure 20. Evaluation Board VCC Layer, View from Top REV.
PAGE 28
AD8152 Figure 21. Evaluation Board VEE Layer, View from Top –28– REV.
PAGE 29
AD8152 Figure 22. Evaluation Board VTTI Layer, View from Top REV.
PAGE 30
AD8152 Figure 23. Evaluation Board VTTO Layer, View from Top –30– REV.
PAGE 31
AD8152 OUTLINE DIMENSIONS 256-Ball Grid Array [SBGA] (BP-256) Dimensions shown in millimeters A1 CORNER 27.00 BSC 20 18 19 16 17 14 15 12 13 10 11 8 9 6 7 4 5 2 3 A B C D E F G H J K L M N P R T U V W Y 1.27 A1 27.00 BSC 24.13 REF TOP 24.13 REF BOTTOM 1.27 1.00 0.80 0.70 0.60 0.60 0.50 0.20 COPLANARITY 0.20 MIN SEATING PLANE 0.90 0.75 0.60 BALL DIAMETER SEATING PLANE 0.25 MIN COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2 REV.
PAGE 32
AD8152 Revision History Location Page 1/03—Data Sheet changed from REV. 0 to REV. A. PRINTED IN U.S.A. C02984–0–1/03(A) Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –32– REV.