Datasheet

REV. A–14–
AD8152
CS
WE
A[6:0]INPUTS
D[5:0]INPUTS
t
CSW
t
ASW
t
WP
t
DSW
t
AHW
t
AHW
t
CHW
t
DHW
Figure 3a. First Rank Write Cycle
Table V. First Rank Write Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSW
Setup Time Chip Select to Write Enable T
A
= 25ⴗC0 ns
t
ASW
Address to Write Enable 0 ns
t
DSW
Data to Write Enable VCC = 3.3 V 1 ns
t
CHW
Hold Time Chip Select from Write Enable 0 ns
t
AHW
Address from Write Enable 0 ns
t
DHW
Data from Write Enable 0 ns
t
WP
Width of Write Enable Pulse 10 ns
CS
UPDATE
ENABLING
OUT[0:33][N:P]
OUTPUTS
TOGGLE
OUT[0:33][N:P]
OUTPUTS
DATA FROM RANK 1
t
CSU
t
UOE
t
UW
t
CHU
DISABLING
OUT[0:33][N:P]
OUTPUTS
t
UOD
DATA FROM RANK 1
DATA FROM RANK 2
PREVIOUS RANK 2 DATA
t
UOT
Figure 3b. Second Rank Update Cycle
Table VI. Second Rank Update Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSU
Setup Time Chip Select to Update T
A
= 25ⴗC0 ns
t
CHU
Hold Time Chip Select from Update 0 ns
t
UOE
Output Enable Times Update to Output Enable VCC = 3.3 V 25 45 ns
t
UOT
Output Toggle Times Update to Output Reprogram 25 45 ns
t
UOD
Output Disable Times Update to Output Disabled 25 45 ns
t
UW
Width of Update Pulse 10 ns