Datasheet

ManualsBrandsANALOG DEVICES ManualsLogic ICsLogic IC - Switch Crosspoint switch Single supply CSPBGA 49 (8x8)

6.25 Gbps, 4 × 4,

Digital Crosspoint Switch with EQ

AD8156

Rev. 0

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FEATURES

4 × 4, fully differential, nonblocking array

Configurable for dual 2 × 2 operation

DC to 6.25 Gbps per channel, NRZ data rate

Programmable input equalization compensates for over 40”

of FR-4 at 6.25 Gbps

Multicast and broadcast modes of operation

Programmable output swing

100 mV p-p to 1.6 V p-p differential

Power supply: 3.3 V (±10%)

Low power

No EQ: 400 mW typical

Maximum EQ: 700 mW typical

Inputs: ac-coupled or dc-coupled

Wide set of dc-coupled input standards

3.3 V/2.5 V/1.8 V CML or 3.3 V LVPECL

Control: LVTTL- or LVCMOS-compatible

Low additive jitter: 25 ps p-p typical

Low random jitter: 0.8 ps rms

Integrated 50 Ω termination impedance at inputs/outputs

Individual output disable for power savings

49-ball, 8 mm × 8 mm BGA, 1 mm pitch

APPLICATIONS

Backplane equalization

SONET/SDH

Gigabit Ethernet

XAUI

Fibre Channel

FUNCTIONAL BLOCK DIAGRAM

RST

UPD

MODE

D[3:0]

A[3:0]

CONTROL

LOGIC

AD8156

IN0P/N

IN1P/N

IN2P/N

IN3P/N

OUT0P/N

OUT1P/N

OUT2P/N

OUT3P/N

OUTPUT

DRIVERS

INPUT

RECEIVERS

INPUT

EQUALIZATION

4 × 4

SWITCH

06305-001

Figure 1.

GENERAL DESCRIPTION

The AD8156, a member of the Xstream line of products, is a

high speed, fully differential, digital crosspoint switch. The part

can function as a 4 × 4 crosspoint switch with double-latched

memory, allowing simultaneous updates, or as a dual 2 × 2 with

direct output control. The AD8156 has low power dissipation,

typically 700 mW on 3.3 V with all outputs and input equalizers

active. It operates at any data rate from dc to 6.25 Gbps per port.

Each input channel on the AD8156 has a programmable input

equalizer to compensate for signal loss over a backplane.

The AD8156 high speed inputs are compatible with both ac-

coupled and dc-coupled 3.3 V, 2.5 V, or 1.8 V CML, as well as

3.3 V LVPECL data levels. The control interface is LVTTL- and

LVCMOS-compatible at 3.3 V. All input and output termination

resistors are integrated for ease of layout and to minimize

impedance mismatch. Input equalization and unused outputs

can be individually disabled to minimize power dissipation.

The AD8156 is packaged in a 49-ball, 8 mm × 8 mm, BGA

package with a 1 mm ball pitch. It operates over the industrial

temperature range of −40°C to 85°C.

Summary of content (20 pages)

PAGE 1
6.25 Gbps, 4 × 4, Digital Crosspoint Switch with EQ AD8156 FEATURES FUNCTIONAL BLOCK DIAGRAM INPUT RECEIVERS INPUT EQUALIZATION AD8156 OUTPUT DRIVERS IN0P/N EQ IN1P/N EQ IN2P/N EQ OUT2P/N IN3P/N EQ OUT3P/N CS RST UPD WE RE MODE 4 D[3:0] 4 A[3:0] OUT0P/N 4×4 SWITCH OUT1P/N CONTROL LOGIC 06305-001 4 × 4, fully differential, nonblocking array Configurable for dual 2 × 2 operation DC to 6.
PAGE 2
AD8156 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications....................................................................................... 1 4 × 4 Mode................................................................................... 13 Functional Block Diagram ...........................................................
PAGE 3
AD8156 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VTTI = VTTO = VCC = 3.3 V, VEE = 0 V, RL = 50 Ω, differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223−1, VIN = 1 V p-p differential, TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
AD8156 TIMING SPECIFICATIONS VTTI = VTTO = VCC = 3.3 V, VEE = 0 V, RL = 50 Ω, differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223 − 1, VIN = 1 V p-p differential, TA = 25°C, unless otherwise noted. Table 2.
PAGE 5
AD8156 TIMING DIAGRAMS CS WE A[3:0] D[3:0] tCSW tCHW tDSW tAHW tWP 06305-002 tASW tDHW Figure 2. First Rank Write Cycle CS UPD OUTxN/P ENABLE OUTxN/P DISABLE OUTxN/P TOGGLE tUW tCSU tCHU tUOD tUOT Figure 3. Second Rank Update Cycle Rev.
PAGE 6
AD8156 CS UPD WE OUTxN/P ENABLE OUTxN/P DISABLE OUTxN/P TOGGLE tWOE tWHU 06305-004 tWOD tWOT Figure 4. Transparent Write and Update Cycle CS RE ADDR1 ADDR2 DATA[3:0] DATA1 tCSR tRDE DATA2 tRHA tAA tCHR tRDD 06305-005 ADDR[3:0] Figure 5. Second Rank Readback Cycle RST tTOD tTW Figure 6. Asynchronous Reset Rev.
PAGE 7
AD8156 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VCC to VEE VTTI VTTO Internal Power Dissipation1 Input Voltage Logic Input Voltage Storage Temperature Range Junction Temperature Lead Temperature Range 1 THERMAL RESISTANCE Rating 3.6 V VCC + 0.6 V VCC + 0.6 V 1.92 W VCC + 0.6 V VEE − 0.3 V < VIN < VCC + 0.6 V −65°C to +125°C 150°C 300°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4.
PAGE 8
AD8156 7 6 5 4 3 2 1 VCC IN0P IN0N VTTI IN1P IN1N VEE A OUT0P VCC MODE VEE D3 VEE IN2P B OUT0N CS WE RST D2 D0 IN2N C VTTO VCC UPD VEE D1 VEE VTTI D OUT1P VCC RE A3 A1 A0 IN3P E OUT1N VEE VEE VEE A2 VCC IN3N F VEE OUT2P OUT2N VTTO OUT3P OUT3N VCC G 06305-007 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 7. Pin Configuration (Bottom View) Table 5. Pin Function Descriptions Pin No. Mnemonic Description Pin No.
PAGE 9
AD8156 TYPICAL PERFORMANCE CHARACTERISTICS 06305-011 06305-008 200mV/DIV 200mV/DIV VTTI = VTTO = VCC = 3.3 V, VEE = 0 V, RL = 50 Ω, differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223 − 1, VIN = 1 V p-p differential, TA = 25°C, unless otherwise noted. 50ps/DIV 50ps/DIV Figure 11. Output Eye Diagram at 3.2 Gbps, 10” FR4, Optimal EQ 06305-009 06305-012 200mV/DIV 200mV/DIV Figure 8. Input Eye Diagram at 3.2 Gbps,10” FR4 50ps/DIV 50ps/DIV Figure 12.
PAGE 10
06305-017 06305-014 200mV/DIV 200mV/DIV AD8156 25ps/DIV 25ps/DIV Figure 17. Output Eye Diagram at 6.25Gbps, 40” FR4, Optimal EQ 35 35 30 30 DETERMINISTIC JITTER (ps) 20 6.25Gbps 15 10 3.2Gbps 0 0.5 0 1.0 1.5 2.0 20 15 10 5 06305-015 5 6.25Gbps 25 0 –40 2.5 DIFFERENTIAL INPUT (V p-p) 30 25 25 EQ GAIN (dB) 30 20 DETERMINISTIC JITTER 5 5 0 3 4 5 40 60 80 15 10 2 20 20 10 06305-016 DETERMINISTIC JITTER (ps p-p) 35 1 0 Figure 18. Deterministic Jitter vs.
PAGE 11
50 800 45 700 40 600 EYE HEIGHT (mV) 35 30 25 20 15 400 300 200 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 50 45 40 35 30 25 20 15 06305-023 10 5 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 Figure 22. Eye Height vs. Data Rate Figure 20. Deterministic Jitter vs. VCC 0 0 DATA RATE (Gbps) VCC (V) 0 100 06305-024 5 DETERMINISTIC JITTER (ps p-p) 500 10 06305-022 DETERMINISTIC JITTER (ps p-p) AD8156 2.5 3.0 3.5 4.0 OUTPUT TERMINATION VOLTAGE (V) Figure 21. Deterministic Jitter vs.
PAGE 12
AD8156 TEST CIRCUIT AD8156 PATTERN GENERATOR FR4 TEST BACKPLANE 50Ω 2 CABLES 2 AC-COUPLED EVALUATION BOARD IN0P/N OUT0P/N IN1P/N DIFFERENTIAL STRIPLINE TRACES 8mils WIDE, 8mils SPACE, AND 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 10", 20", 30", AND 40" IN2P/N OUT1P/N IN3P/N OUT3P/N *SINGLE-ENDED REPRESENTATION OUT2P/N 2 50Ω CABLES 2 50Ω HIGH SPEED SAMPLING OSCILLOSCOPE 2 2 50Ω Figure 23. AD8156 Test Circuit Rev.
PAGE 13
AD8156 THEORY OF OPERATION The AD8156 is a 4 × 4 crosspoint switch with programmable input equalization and programmable output current levels. It can be used as a nonblocking and fully programmable 4 × 4 crosspoint switch, or as a dual 2 × 2 protection switch with fast channel switching. Each lane can run at any rate from dc to 6.25 Gbps independent of the other lanes. If desired for verification, the value of the second bank of latches can be read back by pulling RE low.
PAGE 14
AD8156 When in dual 2 × 2 mode, the A[3:0] and D[3:0] pins set the AD8156 configuration state when CS is low. This configuration method allows the user to have multiple AD8156s share the control bus while each device has its own dedicated CS control signal. INPUT RECEIVERS IN0P/N INPUT EQUALIZATION AD8156 OUTPUT DRIVERS OUT0P/N EQ 2×2 SWITCH IN1P/N EQ IN2P/N EQ EQ IN3P/N OUT1P/N OUT2P/N 2×2 SWITCH OUT3P/N 06305-008 VCC MODE • • • • Peak gain of 23 dB at 3.125 GHz (~6.
PAGE 15
AD8156 CONTROL INTERFACE DESCRIPTION The control interface for the AD8156 consists of a set of address, data, and several control pins. All control pins are active low. The control interface is level sensitive. all outputs are connected but disabled. RST overrides all of the other control pins. CS Pin CONTROL PINS All control pins on the chip are level-sensitive, not edge-triggered.
PAGE 16
AD8156 ADDRESS PINS, A[3:0] INPUTS DATA PINS, D[3:0] INPUTS/OUTPUTS The AD8156 feature sets can be set port by port or globally. A[3:2] specify what is being programmed or read back when the part is being configured port by port. Connectivity, output current, equalization, or global programming features are chosen based on the values of A[3:2]. Similarly, A[1:0] address the port that is being programmed or read back. In global programming, A[1:0] serve a different function.
PAGE 17
AD8156 PROGRAMMING EXAMPLES A[3:0] D[3:0] 06305-009 WE UPD Figure 25. Sample Timing Diagram for 4x4 Mode Programming Examples DUAL 2 × 2 MODE (MODE PIN = 1) PROGRAMMING EXAMPLES Table 9. Dual 2 × 2 Mode Programming A3 1 1 1 1 0 0 1 Address Pins A2 A1 A0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 0 1 1 D3 0 1 0 1 Data Pins D2 D1 x x x x 0 x 0 x D0 x x x x x x 0 x x 1 x 1 1 0 1 0 Description A[3] = 1 enables OUT3. D[3] = 0 connects IN2 to OUT3. A[3] = 1 enables OUT3. D[3] = 1 connects IN3 to OUT3.
PAGE 18
AD8156 Table 12. Broadcast Connectivity Programming, A[3:0] = b1000 A3 1 1 1 Address Pins A2 A1 0 0 0 0 0 0 A0 0 0 0 D3 0 0 0 Data Pins D2 D1 1 0 1 1 0 1 D0 0 1 0 Description D2 = 1 enables all outputs. D[1:0] = b00 connects IN0 to all outputs. D2 = 1 enables all outputs. D[1:0] = b11 connects IN3 to all outputs. D2 = 0 disables all outputs. D[1:0] = b10 connects IN2 to all outputs, but all outputs are disabled. Table 13.
PAGE 19
AD8156 OUTLINE DIMENSIONS 8.20 8.00 SQ 7.80 A1 CORNER INDEX AREA 7 6 5 4 3 2 1 A BALL A1 PAD CORNER TOP VIEW B C 6.00 BSC SQ D E F G 1.00 BSC DETAIL A BOTTOM VIEW DETAILA 0.25 MIN 0.70 0.60 0.50 BALL DIAMETER SEATING PLANE *1.31 1.21 1.10 COPLANARITY 0.20 *COMPLIANT WITH JEDEC STANDARDS MO-192-ABB-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. 012006-0 *1.85 1.71 1.50 Figure 26.