Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Video editing Video switcher LQFP 100 (14x14)

4:1 HDMI/DVI Switch with Equalization

AD8197B

Rev. 0

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rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

4 inputs, 1 output HDMI/DVI links

Enables HDMI 1.3-compliant receiver

Pin-to-pin compatible with the AD8197A

4 TMDS channels per link

Supports 250 Mbps to 2.25 Gbps data rates

Supports 25 MHz to 225 MHz pixel clocks

Equalized inputs allow use of long HDMI cables

(20 meters at 2.25 Gbps)

Fully buffered unidirectional inputs/outputs

Per input switchable, 50 Ω on-chip terminations

Switchable output 50 Ω on-chip terminations

Pre-emphasized outputs

Low added jitter

Single-supply operation (3.3 V)

4 auxiliary channels per link

Bidirectional unbuffered inputs/outputs

Flexible supply operation (3.3 V to 5 V)

HDCP standard compatible

Allows switching of DDC bus and 2 additional signals

Output disable feature

Reduced power dissipation

Removable output termination

Allows building of larger arrays

Two AD8197Bs support HDMI/DVI dual link

Standards compatible: HDMI receiver, HDCP, DVI

Serial (I

C slave) and parallel control interface

100-lead, 14 mm × 14 mm LQFP, Pb-free package

APPLICATIONS

Multiple input displays

Projectors

A/V receivers

Set-top boxes

Advanced television (HDTV) sets

TYPICAL APPLICATION

DVD PLAYER

GAME CONSOLE

SET-TOP BOX

MEDIA CENTER

HDTV SET

HDMI

RECEIVER

AD8197B

04:20

07015-002

Figure 1. Typical HDTV Application

FUNCTIONAL BLOCK DIAGRAM

LOW SPEED UNBUFFERED

HIGH SPEED BUFFERED

AVCC

DVCC

AMUXVCC

AVEE

DVEE

VTTO

OP[3:0]

AUX_COM[3:0]

ON[3:0]

–

BIDIRECTIONAL

I2C_SDA

I2C_SCL

I2C_ADDR[2:0]

VTTI

IP_A[3:0]

IN_A[3:0]

–

IP_B[3:0]

IN_B[3:0]

–

IP_C[3:0]

IN_C[3:0]

–

IP_D[3:0]

IN_D[3:0]

AUX_C[3:0]

AUX_B[3:0]

AUX_A[3:0]

AUX_D[3:0]

–

SWITCH

CORE

SWITCH

CORE

CONTROL

LOGIC

CONFIG

INTERFACE

2 2

SERIAL

PARALLEL

PP_CH[1:0]

PP_OTO

PP_OCL

PP_EQ

PP_EN

PP_PRE[1:0]

RESET

AD8197B

07015-001

Figure 2.

GENERAL DESCRIPTION

The AD8197B is an HDMI™/DVI switch featuring equalized

TMDS® inputs and pre-emphasized TMDS outputs, ideal for

systems with long cable runs. The AD8197B offers individual

control of the on/off state of the TMDS input termination

resistors via I

C® control. Outputs can be set to a high

impedance state to reduce the power dissipation and/or to allow

the construction of larger arrays using the wire-OR technique.

The AD8197B is provided in a 100-lead LQFP, Pb-free, surface-

mount package, specified to operate over the −40°C to +85°C

temperature range.

PRODUCT HIGHLIGHTS

1. Supports data rates up to 2.25 Gbps, enabling 1080p deep

color (12-bit color) HDMI formats and greater than UXGA

(1600 × 1200) DVI resolutions.

2. Input cable equalizer enables use of long cables at the input

(more than 20 meters of 24 AWG cable at 2.25 Gbps).

3. Auxiliary switch routes a DDC bus and two additional signals

for a single-chip, HDMI 1.3 receive-compliant solution.

Summary of content (28 pages)

PAGE 1
4:1 HDMI/DVI Switch with Equalization AD8197B FUNCTIONAL BLOCK DIAGRAM PP_CH[1:0] PP_OTO PP_OCL PP_EQ PP_EN PP_PRE[1:0] 4 inputs, 1 output HDMI/DVI links Enables HDMI 1.3-compliant receiver Pin-to-pin compatible with the AD8197A 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs allow use of long HDMI cables (20 meters at 2.
PAGE 2
AD8197B TABLE OF CONTENTS Features .............................................................................................. 1 Switching/Update Delay............................................................ 16 Applications....................................................................................... 1 Parallel Control Interface .............................................................. 17 Typical Application...........................................................................
PAGE 3
AD8197B SPECIFICATIONS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. Table 1.
PAGE 4
AD8197B Parameter SERIAL CONTROL INTERFACE 5 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL PARALLEL CONTROL INTERFACE Input High Voltage, VIH Input Low Voltage, VIL Conditions/Comments Min Typ Max 2 0.4 V V V V 0.8 V V 0.8 2.4 2 1 Unit Differential interpair skew is measured between the TMDS pairs of a single link. AD8197B output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
PAGE 5
AD8197B ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter AVCC to AVEE DVCC to DVEE DVEE to AVEE VTTI VTTO AMUXVCC Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Low Speed Input Voltage I2C and Parallel Logic Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Rating 3.7 V 3.7 V ±0.3 V AVCC + 0.6 V AVCC + 0.6 V 5.5 V 2.2 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V DVEE − 0.3 V < VIN < AMUXVCC + 0.6 V DVEE − 0.
PAGE 6
AD8197B 75 AVCC 74 IP_C3 AUX_A1 AUX_A2 AUX_A3 DVEE AUX_B0 AUX_B1 AUX_B2 AUX_B3 AUX_COM0 AUX_COM1 AUX_COM2 AUX_COM3 AUX_C0 AUX_C1 AUX_C2 AUX_C3 AMUXVCC AUX_D0 AUX_D1 AUX_D2 AUX_D3 PP_EQ PP_EN 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVCC 1 IN_B0 2 IP_B0 3 73 IN_C3 AVEE 4 72 AVEE IP_C2 PIN 1 INDICATOR IN_B1 5 71 IP_B1 6 70 IN_C2 VTTI 7 69 VTTI IP_C1 IN_B2 8 68 IP_B2 9 67 IN_C1 AVEE 10 66 AVEE IN_B3 1
PAGE 7
AD8197B Pin No.
PAGE 8
AD8197B Pin No. 89 90 91 92 93 94 96 97 98 99 100 1 Mnemonic AUX_COM1 AUX_COM0 AUX_B3 AUX_B2 AUX_B1 AUX_B0 AUX_A3 AUX_A2 AUX_A1 AUX_A0 PP_OTO Type 1 LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O Control Description Low Speed Common Input/Output. Low Speed Common Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output.
PAGE 9
AD8197B TYPICAL PERFORMANCE CHARACTERISTICS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless otherwise noted. HDMI CABLE AD8197B DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07015-004 SMA COAX CABLE 0.125UI/DIV AT 2.25Gbps 0.
PAGE 10
AD8197B TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless otherwise noted. HDMI CABLE AD8197B DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07015-009 SMA COAX CABLE 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps 07015-013 0.
PAGE 11
AD8197B TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless otherwise noted. 0.6 0.6 2m CABLE = 30AWG 5m TO 20m CABLES = 24AWG 2m CABLE = 30AWG 5m TO 20m CABLES = 24AWG 0.5 0.4 DETERMINISTIC JITTER (UI) DETERMINISTIC JITTER (UI) 0.5 2.25Gbps EQ = 12dB 0.3 1.65Gbps EQ = 6dB 2.25Gbps EQ = 6dB 0.
PAGE 12
AD8197B 50 50 40 40 30 30 JITTER (ps) DJ (p-p) 20 10 DJ (p-p) 20 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DIFFERENTIAL INPUT SWING (V) 07015-020 0 0 2.5 3.5 3.7 115 DIFFERENTIAL INPUT TERMINATION RESISTANCE (Ω) 40 35 JITTER (ps) 3.3 120 45 30 25 DJ (p-p) 20 15 10 5 0 20 40 60 80 100 Figure 21. Jitter vs. Temperature FALL TIME 120 RISE TIME 100 80 60 40 40 60 80 TEMPERATURE (°C) 100 07015-022 20 20 95 90 –20 0 20 40 60 80 100 Figure 24.
PAGE 13
AD8197B THEORY OF OPERATION The AD8197B is a pin-to-pin HDMI 1.3 receive-compliant replacement for the AD8197A. The primary function of the AD8197B is to switch one of four (HDMI or DVI) single link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary singleended, low speed control signals.
PAGE 14
AD8197B VTTO 50Ω When turning off the AD8197B, care needs to be taken with the AMUXVCC supply to ensure that the auxiliary multiplexer pins remain in a high impedance state. A scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel (DDC) bus. In some applications, additional devices can be connected to the DDC bus (such as an EEPROM with EDID information) upstream of the AD8197B. 50Ω OPx ONx IOUT 07015-025 DISABLE AVEE Figure 26.
PAGE 15
AD8197B SERIAL CONTROL INTERFACE RESET 3. Send the write indicator bit (0). On initial power-up, or at any point in operation, the AD8197B register set can be restored to the status of the parallel control interface pins and some preprogrammed default values by pulling the RESET pin to low, in accordance with the specifications in Table 1. During normal operation, however, the RESET pin must be pulled up to 3.3 V.
PAGE 16
AD8197B I2C_SCL R/W GENERAL CASE I2C_SDA START FIXED PART ADDR R/W REGISTER ADDR ADDR SR ACK FIXED PART ADDR ACK DATA ADDR STOP ACK ACK 9 10 11 12 1 2 3 4 5 6 7 8 13 07015-029 EXAMPLE I2C_SDA 2 Figure 30. I C Read Diagram 13. Perform one of the following: READ PROCEDURE 2 13a. Send a stop condition (while holding the I2C_SCL line high, pull the SDA line high) and release control of the bus to end the transaction (shown in Figure 30).
PAGE 17
AD8197B PARALLEL CONTROL INTERFACE The AD8197B can be partially controlled through the parallel interface using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 18.
PAGE 18
AD8197B SERIAL INTERFACE CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I2C serial control interface, Pin I2C_SDA, and Pin I2C_SCL. The least significant bits of the AD8197B I2C part address are set by tying the Pin I2C_ADDR2, Pin I2C_ADDR1, and Pin I2C_ADDR0 to 3.3 V (Logic 1) or 0 V (Logic 0).
PAGE 19
AD8197B HIGH SPEED DEVICE MODES REGISTER INPUT TERMINATION SELECT REGISTER 1 AND REGISTER 2 HS_EN: High Speed (TMDS) Channels Enable Bit Table 6. HS_EN Description HS_EN 0 1 Description High speed channels off, low power/standby mode High speed channels on HS_CH[1:0]: High Speed (TMDS) Switch Source Select Bus Table 7.
PAGE 20
AD8197B TRANSMITTER SETTINGS REGISTER TX_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis Level Select Bus (For All TMDS Channels) Table 15. TX_PE[1:0] Description TX_PE[1:0] 00 01 10 11 Description No pre-emphasis (0 dB) Low pre-emphasis (2 dB) Medium pre-emphasis (4 dB) High pre-emphasis (6 dB) TX_PTO: High Speed (TMDS) Output Termination On/Off Select Bit (For All Channels) Table 16.
PAGE 21
AD8197B PARALLEL INTERFACE CONFIGURATION REGISTERS The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. This interface is accessible only after the part is reset and before any registers are accessed using the serial control interface.
PAGE 22
AD8197B HIGH SPEED DEVICE MODES REGISTER RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 PP_EN: High Speed (TMDS) Channels Enable Bit PP_EQ: High Speed (TMDS) Inputs Equalization Level Select Bit (For All TMDS Input Channels) Table 19. PP_EN Description PP_EN 0 1 Description High speed channels off, low power/standby mode High speed channels on PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus Table 20.
PAGE 23
AD8197B 07015-030 APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8197B Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8197B is an HDMI/DVI switch, featuring equalized TMDS inputs and pre-emphasized TMDS outputs. It is intended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output, and is fully HDMI 1.3 receive-compliant.
PAGE 24
AD8197B The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors, including: • Cable quality: the quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors have lower signal degradation per unit length. • Data rate: the data rate being sent over the cable. The signal degradation of HDMI cables increases with data rate. • Edge rates: the edge rates of the source input.
PAGE 25
AD8197B Both traces of a given differential pair must be equal in length to minimize intrapair skew. Maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (DCD). The p and n of a given differential pair should always be routed together to establish the required 100 Ω differential impedance.
PAGE 26
AD8197B the AD8197B and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general, it is sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the PCB. However, it is best to follow strict layout practices whenever possible to prevent the PCB design from affecting the overall application.
PAGE 27
AD8197B Power Supply Bypassing The AD8197B requires minimal supply bypassing. When powering the supplies individually, place a 0.01 μF capacitor between each 3.3 V supply pin (AVCC, DVCC, VTTI, and VTTO) and ground to filter out supply noise. Generally, bypass capacitors should be placed near the power pins and should connect directly to the relevant supplies (without long intervening traces).
PAGE 28
AD8197B OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BED 051706-A 1.45 1.40 1.35 Figure 36.