Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - In-amp InAmp MSOP 10

10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS

Programmable Gain Instrumentation Amplifier

Data Sheet

AD8253

Rev. B Document Feedback

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FEATURES

Small package: 10-lead MSOP

Programmable gains: 1, 10, 100, 1000

Digital or pin-programmable gain setting

Wide supply: ±5 V to ±15 V

Excellent dc performance

High CMRR: 100 dB (minimum), G = 100

Low gain drift: 10 ppm/°C (maximum)

Low offset drift: 1.2 V/°C (maximum), G = 1000

Excellent ac performance

Fast settling time: 780 ns to 0.001% (maximum)

High slew rate: 20 V/µs (minimum)

Low distortion: −110 dB THD at 1 kHz,10 V swing

High CMRR over frequency: 100 dB to 20 kHz (minimum)

Low noise: 10 nV/√Hz, G = 1000 (maximum)

Low power: 4 mA

APPLICATIONS

Data acquisition

Biomedical analysis

Test and measurement

GENERAL DESCRIPTION

The AD8253 is an instrumentation amplifier with digitally

programmable gains that has gigaohm (GΩ) input impedance,

low output noise, and low distortion, making it suitable for

interfacing with sensors and driving high sample rate analog-to-

digital converters (ADCs).

It has a high bandwidth of 10 MHz, low THD of −110 dB, and

fast settling time of 780 ns (maximum) to 0.001%. Offset drift and

gain drift are guaranteed to 1.2 V/°C and 10 ppm/°C, respectively,

for G = 1000. In addition to its wide input common voltage range,

it boasts a high common-mode rejection of 100 dB at G = 1000

from dc to 20 kHz. The combination of precision dc performance

coupled with high speed capabilities makes the AD8253 an

excellent candidate for data acquisition. Furthermore, this

monolithic solution simplifies design and manufacturing and

boosts performance of instrumentation by maintaining a tight

match of internal resistors and amplifiers.

The AD8253 user interface consists of a parallel port that allows

users to set the gain in one of two different ways (see Figure 1

for the functional block diagram). A 2-bit word sent via a bus

can be latched using the

input. An alternative is to use

transparent gain mode, where the state of logic levels at the gain

port determines the gain.

FUNCTIONAL BLOCK DIAGRAM

A1 A0DGND WR

AD8253

–V

REF

OUT

+IN

LOGIC

–IN

8 3

4562

06983-001

Figure 1.

–10

–20

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

GAIN (dB)

006983-023

G = 1000

G = 100

G = 10

G = 1

Figure 2. Gain vs. Frequency

Table 1. Instrumentation Amplifiers by Category

General

Purpose

Zero

Drift

Mil

Grade

Low

Power

High Speed

PGA

AD8220

AD8231

AD620 AD627

AD8250

AD8221 AD8553

AD621 AD623

AD8251

AD8222 AD8555

AD524 AD8223

AD8253

AD8224

AD8556

AD526

AD8228 AD8557

AD624

Rail-to-rail output.

The AD8253 is available in a 10-lead MSOP package and is

specified over the −40°C to +85°C temperature range, making it

an excellent solution for applications where size and packing

density are important considerations.

Summary of content (24 pages)

PAGE 1
0 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier AD8253 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR Small package: 10-lead MSOP Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.2 μV/°C (maximum), G = 1000 Excellent ac performance Fast settling time: 780 ns to 0.
PAGE 2
AD8253 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Regulation and Bypassing ................................ 18 Applications ....................................................................................... 1 Input Bias Current Return Path ............................................... 18 General Description .........................................................................
PAGE 3
Data Sheet AD8253 SPECIFICATIONS +VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR to 20 kHz1 G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz, RTI G=1 G = 10 G = 100 G = 1000 0.1 Hz to 10 Hz, RTI G=1 G = 10 G = 100 G = 1000 Current Noise, 1 kHz Current Noise, 0.
PAGE 4
AD8253 Parameter Settling Time 0.001% G=1 G = 10 G =100 G = 1000 Slew Rate G=1 G = 10 G = 100 G = 1000 Total Harmonic Distortion + Noise GAIN Gain Range Gain Error G=1 G = 10, 100, 1000 Gain Nonlinearity G=1 G = 10 G = 100 G = 1000 Gain vs.
PAGE 5
Data Sheet AD8253 Parameter POWER SUPPLY Operating Range Quiescent Current, +IS Quiescent Current, −IS Over Temperature TEMPERATURE RANGE Specified Performance Conditions Min Typ Max Unit 4.6 4.5 ±15 5.3 5.3 6 V mA mA mA +85 °C ±5 T = −40°C to +85°C −40 1 See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency. Input bias current over temperature: minimum at hot and maximum at cold. 3 See Figure 30 for input voltage limit vs.
PAGE 6
AD8253 Data Sheet ABSOLUTE MAXIMUM RATINGS power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some of which is dissipated in the load (VOUT × IOUT). Table 3.
PAGE 7
Data Sheet AD8253 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 DGND 2 10 +IN AD8253 9 REF 8 +VS TOP VIEW A0 4 (Not to Scale) 7 OUT A1 5 6 WR 06983-005 –VS 3 Figure 5. 10-Lead MSOP (RM-10) Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic −IN DGND −VS A0 A1 WR OUT +VS REF +IN Description Inverting Input Terminal. True differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable.
PAGE 8
AD8253 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 210 240 180 150 NUMBER OF UNITS NUMBER OF UNITS 210 120 90 180 150 120 90 60 60 30 –60 –40 –20 0 0 06983-006 0 20 CMRR (µV/V) –60 –40 –20 0 20 40 60 INPUT OFFSET CURRENT (nA) Figure 6. Typical Distribution of CMRR, G = 1 06983-009 30 Figure 9.
PAGE 9
Data Sheet AD8253 18 16 14 12 10 8 6 4 2 0 0.01 0.1 1 WARM-UP TIME (Minutes) Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000 Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000 140 18 16 120 G = 1000 G = 100 14 100 PSRR (dB) 12 10 8 6 80 G=1 60 G = 10 40 4 10 100 1k 10k 100k FREQUENCY (Hz) 0 10 100 1k 10k 100k 1M 06983-016 1 06983-013 0 1M 06983-017 20 2 FREQUENCY (Hz) Figure 16. Positive PSRR vs. Frequency, RTI Figure 13.
PAGE 10
AD8253 Data Sheet 10.5 IB– 7.5 –20 6.0 –30 4.5 IOS –40 3.0 –50 1.5 –60 –15 –10 –5 0 5 COMMON-MODE VOLTAGE (V) 0 15 10 G = 100 60 G = 10 40 20 G=1 0 10 100 1k 10k 100k 1M 130 FREQUENCY (Hz) Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 18. Input Bias Current and Offset Current vs.
PAGE 11
AD8253 40 400 30 300 NONLINEARITY (10 ppm/DIV) 20 10 0 –10 –20 –6 –4 –2 0 2 4 6 8 10 –200 –400 –10 30 12 INPUT COMMON-MODE VOLTAGE (V) 16 20 10 0 –10 –20 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 25. Gain Nonlinearity, G = 10, RL = 10 kΩ, 2 kΩ, 600 Ω 8 0 –20 –40 4 6 8 10 –8 10 OUTPUT VOLTAGE (V) Figure 26. Gain Nonlinearity, G = 100, RL = 10 kΩ, 2 kΩ, 600 Ω VS, ±15V –14.1V, +7.3V +13.8V, +7.3V 0V, +3.8V +3.8V, +1.9V VS = ±5V +3.8V, –1.9V 0V, –4.2V –14.
PAGE 12
AD8253 Data Sheet +VS +85°C –0.2 –2 +25°C –40°C +2 +25°C –40°C +1 +125°C –VS 4 8 10 12 16 14 Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ 25 +IN –IN –IN –40°C –40°C +25°C +85°C +0.8 +0.6 +0.4 +125°C –VS 4 6 8 10 12 16 14 SUPPLY VOLTAGE (±VS) Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, RL = 10 kΩ +25°C 10 5 +IN +25°C +1.0 OUTPUT VOLTAGE SWING (V) CURRENT (mA) +85°C +85°C +Vs –5 –10 –1.
PAGE 13
Data Sheet AD8253 5V/DIV NO LOAD 47pF 100pF 1392ns TO 0.01% 1712ns TO 0.001% 2µs/DIV 2µs/DIV TIME (µs) Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1 06983-039 20mV/DIV 06983-036 0.002%/DIV Figure 39. Large-Signal Pulse Response and Settling Time, G = 100, RL = 10 kΩ 5V/DIV 664ns TO 0.01% 744ns TO 0.001% 0.002%/DIV 0.002%/DIV TIME (µs) 10µs/DIV 06983-037 2µs/DIV 12.88µs TO 0.01% 16.64µs TO 0.001% TIME (µs) Figure 37.
PAGE 14
AD8253 Data Sheet 1400 1200 1000 TIME (ns) SETTLED TO 0.001% 800 600 SETTLED TO 0.01% 400 2 4 6 8 10 12 14 16 18 20 06983-045 0 20 06983-046 200 20 06983-047 2µs/DIV 06983-042 20mV/DIV STEP SIZE (V) Figure 42. Small-Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF Figure 45. Settling Time vs. Step Size, G = 1, RL = 10 kΩ 1400 1200 TIME (ns) 1000 SETTLED TO 0.001% 800 SETTLED TO 0.
PAGE 15
Data Sheet AD8253 0 20 18 –10 SETTLED TO 0.001% –20 16 –30 –40 12 THD + N (dB) SETTLED TO 0.01% 10 8 –50 G = 1000 –60 G = 100 –70 G = 10 –80 6 –90 4 –110 0 –120 10 2 4 6 8 10 12 14 16 18 20 06983-048 2 STEP SIZE (V) 0 –20 –30 –40 –50 G = 1000 –70 G = 100 –80 G = 10 –90 –100 G=1 100 1k 10k 100k FREQUENCY (Hz) 1M 06983-049 –110 –120 10 1k 10k 100k Figure 50. Total Harmonic Distortion vs.
PAGE 16
AD8253 Data Sheet THEORY OF OPERATION +VS +VS A0 A1 2.2kΩ +VS –VS –VS 1.2kΩ –IN 10kΩ A1 10kΩ –VS +VS DIGITAL GAIN CONTROL OUT A3 –VS +VS +VS +IN 10kΩ A2 +VS –VS 10kΩ REF –VS +VS 2.2kΩ DGND WR –VS 06983-061 1.2kΩ –VS Figure 51. Simplified Schematic The AD8253 is a monolithic instrumentation amplifier based on the classic 3-op-amp topology, as shown in Figure 51. It is fabricated on the Analog Devices, Inc.
PAGE 17
Data Sheet AD8253 Table 5. Truth Table Logic Levels for Transparent Gain Mode Table 6. Truth Table Logic Levels for Latched Gain Mode WR WR A1 Low Low High High −VS −VS −VS −VS A0 Low High Low High Gain 1 10 100 1000 Latched Gain Mode Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus.
PAGE 18
AD8253 Data Sheet INCORRECT POWER SUPPLY REGULATION AND BYPASSING The AD8253 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier.
PAGE 19
Data Sheet AD8253 REFERENCE TERMINAL Coupling Noise The reference terminal, REF, is at one end of a 10 kΩ resistor (see Figure 51). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8253 can interface with a single-supply ADC.
PAGE 20
AD8253 Data Sheet +15V 10µF CC R +IN VOUT AD8253 CD R REF –IN CC 0.1µF –15V 06983-057 10µF +15V Figure 58. RFI Suppression 10μF Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at negative input degrades the CMRR of the AD8253. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved. DRIVING AN ANALOG-TO-DIGITAL CONVERTER 0.
PAGE 21
Data Sheet AD8253 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER +15V In certain applications, it is necessary to create a differential signal. High resolution analog-to-digital converters often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. 10μF 0.1µF WR A1 A0 +IN Figure 61 shows how to configure the AD8253 to output a differential signal.
PAGE 22
Data Sheet DATA ACQUISITION AMPLITUDE (dB) The AD8253 makes an excellent instrumentation amplifier for use in data acquisition systems. Its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit ADCs. Figure 63 shows the AD825x as part of a total data acquisition system. The quick slew rate of the AD8253 allows it to condition rapidly changing signals from the multiplexed inputs. An FPGA controls the AD7612, AD8253, and ADG1209.
PAGE 23
Data Sheet AD8253 OUTLINE DIMENSIONS 3.10 3.00 2.90 3.10 3.00 2.90 10 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.70 0.55 0.40 0.23 0.13 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 64.