Datasheet

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Low Cost, DC to 500 MHz, 92 dB

Logarithmic Amplifier

Data Sheet

AD8307

Rev. F Document Feedback

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FEATURES

Complete multistage logarithmic amplifier

92 dB dynamic range: −75 dBm to +17 dBm to −90 dBm

using matching network

Single supply of 2.7 V minimum at 7.5 mA typical

DC to 500 MHz operation, ±1 dB linearity

Slope of 25 mV/dB, intercept of −84 dBm

Highly stable scaling over temperature

Fully differential dc-coupled signal path

100 ns power-up time, 150 A sleep current

APPLICATIONS

Conversion of signal level to decibel form

Transmitter antenna power measurement

Receiver signal strength indication (RSSI)

Low cost radar and sonar signal processing

Network and spectrum analyzers (to 120 dB)

Signal level determination down to 20 Hz

True decibel ac mode for multimeters

FUNCTIONAL BLOCK DIAGRAM

BAND GAP REFERENCE

AND BIASING

SIX 14.3dB 900MHz

AMPLIFIER STAGES

MIRROR

INPUT-OFFSET

COMPENSATION LOOP

COM

INM

INP

ENBVPS

INT

OUT

OFS

AD8307

7.5mA

1.1kΩ

2µA

/dB

12.5kΩ

COM

NINE DETECTOR CELLS

SPACED 14.3dB

–INP

+INP

1082-001

Figure 1.

GENERAL DESCRIPTION

The AD8307 is the first logarithmic amplifier made available in

an 8-lead SOIC_N package. It is a complete 500 MHz monolithic

demodulating logarithmic amplifier based on the progressive

compression (successive detection) technique, providing a

dynamic range of 92 dB to ±3 dB law conformance and 88 dB

to a tight ±1 dB error bound at all frequencies up to 100 MHz.

The AD8307 is extremely stable and easy to use, requiring no

significant external components. A single-supply voltage of

2.7 V to 5.5 V at 7.5 mA is needed. A fast acting CMOS-

compatible control pin can disable the AD8307 to a standby

current of 150 µA.

The AD8307 operates over the industrial temperature range of

−40°C to +85°C and is available in an 8-lead SOIC package and

an 8-lead PDIP.

Table 1. Next Generation Upgrades for the AD8307

Device No. Product Description

AD8310 15 ns Response Time, Buffered Output

ADL5513

Lower Input Range (80 dB), Operation to 4 GHz,

Higher Power Consumption

AD8309 Higher Input Range (100 dB), Limiter Output

Summary of content (24 pages)

PAGE 1
Low Cost, DC to 500 MHz, 92 dB Logarithmic Amplifier AD8307 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Complete multistage logarithmic amplifier 92 dB dynamic range: −75 dBm to +17 dBm to −90 dBm using matching network Single supply of 2.7 V minimum at 7.5 mA typical DC to 500 MHz operation, ±1 dB linearity Slope of 25 mV/dB, intercept of −84 dBm Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 150 μA sleep current AD8307 7.
PAGE 2
AD8307 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Enable Interface .......................................................................... 14 Applications ....................................................................................... 1 Input Interface ............................................................................ 14 Functional Block Diagram .............................................
PAGE 3
Data Sheet AD8307 SPECIFICATIONS VS = 5 V, TA = 25°C, RL ≥ 1 MΩ, unless otherwise noted. Table 2. Parameter GENERAL CHARACTERISTICS Input Range (±3 dB Error) Input Range (±1 dB Error) Logarithmic Conformance Logarithmic Slope vs. Temperature Logarithmic Intercept vs.
PAGE 4
AD8307 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Input Voltage (Pin 1 and Pin 8) Storage Temperature Range (N, R) Ambient Temperature Range, Rated Performance Industrial, AD8307AN, AD8307AR Lead Temperature Range (Soldering, 10 sec) Ratings 7.5 V VSUPPLY −65°C to +125°C −40°C to +85°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product.
PAGE 5
Data Sheet AD8307 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INM 1 8 INP COM 2 7 VPS AD8307 6 ENB TOP VIEW OUT 4 (Not to Scale) 5 INT 01082-002 OFS 3 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic INM COM OFS OUT INT ENB VPS INP Description Signal Input Minus Polarity. Normally at VPOS/2. Common Pin (Usually Grounded). Offset Adjustment. External capacitor connection. Logarithmic (RSSI) Output Voltage. ROUT = 12.5 kΩ.
PAGE 6
AD8307 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 8 3 7 1 5 ERROR (dB) 4 3 TEMPERATURE ERROR @ +85°C 0 TEMPERATURE ERROR @ +25°C –1 TEMPERATURE ERROR @ –40°C 2 –2 0 1.0 01082-003 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 –3 –80 2.0 01082-006 SUPPLY CURRENT (mA) 2 6 –60 VENB (V) –40 –20 0 20 INPUT LEVEL (dBm) Figure 3. Supply Current vs. VENB (5 V) Figure 6. Log Conformance vs.
PAGE 7
Data Sheet AD8307 3.0 3 100MHz INT PIN = 3.0V 10MHz, INT = –96.52dBm 2.5 2 1 ERROR (dB) INT PIN = 4.0V 10MHz, INT = –87.71dBm 1.5 NO CONNECT ON INT 10MHz, INT = –82.90dBm 1.0 +INPUT 0 –1 0.5 –INPUT 01082-009 –2 0 –80 –70 –60 –50 –40 –30 –20 –10 0 10 01082-012 VOUT (V) 2.0 –3 –80 20 –60 INPUT LEVEL (dBm) 3.0 0 20 3 2 INT VOLTAGE INT = 1.0V, INT = –86dBm 500MHz 1 ERROR (dB) INT VOLTAGE INT NO CONNECT, INT = –71dBm 1.5 1.
PAGE 8
AD8307 Data Sheet 2V VOUT CH 1 CH1 200mV VOUT CH1 CH1 500mV CH1 GND 500ns CH2 2.00V CH2 GND 01082-015 GND INPUT SIGNAL CH2 200ns CH2 1.00V Figure 18. VOUT Rise Time Figure 15. Power-Up Response Time VOUT CH 1 01082-018 VENB CH 2 CH1 500mV CH1 200mV 2.5V INPUT SIGNAL CH2 VENB CH 2 CH2 GND VOUT CH1 01082-016 GND 500ns Figure 19. Large Signal Response Time Figure 16. Power-Down Response Time HP8648B 10MHz REF CLK SIGNAL GENERATOR PULSE MODE IN PULSE VPS = 5.0V MODULATION MODE 0.
PAGE 9
Data Sheet AD8307 LOG AMP THEORY Logarithmic amplifiers perform a more complex operation than that of classical linear amplifiers, and their circuitry is significantly different. A good grasp of what log amps do and how they work can prevent many pitfalls in their application. The essential purpose of a log amp is not to amplify, though amplification is utilized to achieve the function. Rather, it is to compress a signal of wide dynamic range to its decibel equivalent. It is thus a measurement device.
PAGE 10
Data Sheet just dB. The logarithmic function disappears from the formula because the conversion has already been implicitly performed in stating the input in decibels. This is strictly a concession to popular convention; log amps manifestly do not respond to power (tacitly, power absorbed at the input), but rather to input voltage. The use of dBV (decibels with respect to 1 V rms) is more precise, though still incomplete, because waveform is involved as well.
PAGE 11
Data Sheet AD8307 Further analysis shows that right up to the point where the input to the first cell is above the knee voltage, VOUT changes by (A − 1)EK for a ratio change of A in VIN. This can be expressed as a certain fraction of a decade, which is simply log10(A). For example, when A = 5, a transition in the piecewise linear output function occurs at regular intervals of 0.7 decade (log10(A), or 14 dB divided by 20 dB).
PAGE 12
AD8307 Data Sheet A/0 gm A/0 gm A3VIN A/0 gm A4VIN gm variation of EK. Do this by adding an offset with the required temperature behavior. VLIM A/0 gm IOUT 01082-026 A2VIN AVIN VIN Figure 26. Log Amp Using A/0 Stages and Auxiliary Summing Cells The chief advantage of this approach is that the slope voltage can now be decoupled from the knee voltage, EK = 2 kT/q, which is inherently PTAT.
PAGE 13
Data Sheet AD8307 In the AD8307, this is achieved by an on-chip filter, providing sufficient suppression of HF feedback to allow operation above 1 MHz. To extend the range below this frequency, an external capacitor can be added. This permits the high-pass corner to be lowered to audio frequencies using a capacitor of modest value.
PAGE 14
AD8307 Data Sheet INTERFACES The differential current-mode outputs of the nine detectors are summed and then converted to single-sided form in the output stage, nominally scaled 2 μA/dB. The logarithmic output voltage is developed by applying this current to an on-chip 12.5 kΩ resistor, resulting in a logarithmic slope of 25 mV/dB (that is, 500 mV/decade) at the OUT pin.
PAGE 15
Data Sheet AD8307 voltage that can block the lower reaches of the dynamic range until it has become much less than the signal. 7 VPS 125Ω INPUT STAGE 125Ω MAIN GAIN STAGES TO LAST DETECTOR In most applications, the signal is single sided and can be applied to either Pin 1 or Pin 8, with the other pin ac-coupled to ground.
PAGE 16
AD8307 Data Sheet 3pF LGP 2µA/dB 0µA TO 220µA 25mV/dB OUT 4 Rev. F | Page 16 of 24 CFLT VPS 5 INT 2 COM ~400mV 60kΩ 1.25kΩ 1.25kΩ C2 1pF C1 2.5pF 7 8.25kΩ 1.25kΩ FROM ALL DETECTORS LGM Note that while the AD8307 can operate down to supply voltages of 2.7 V, the output voltage limit is reduced when the supply drops below 4 V. This characteristic is the result of necessary headroom requirements, approximately two VBE drops, in the design of the output stage. 1.25kΩ R1 12.5kΩ Figure 31.
PAGE 17
Data Sheet AD8307 THEORY OF OPERATION BASIC CONNECTIONS Figure 32 shows the simple connections suitable for many applications. The inputs are ac coupled by C1 and C2, which should have the same value, for example, CC. The coupling time constant is RIN CC/2, thus forming a high-pass corner with a 3 dB attenuation at fHP = 1/(pRINCC ). In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals.
PAGE 18
AD8307 Data Sheet 0.1µF INPUT MATCHING Where higher sensitivity is required, an input matching network is valuable. Using a transformer to achieve the impedance transformation also eliminates the need for coupling capacitors, which lowers the offset voltage generated directly at the input, and balances the drives to the INP pin and the INM pin. The choice of turns ratio depends somewhat on the frequency.
PAGE 19
Data Sheet AD8307 Where higher calibration accuracy is needed, the adjustments shown in Figure 37 can be used, either singly or in combination. The log slope is lowered to 20 mV/dB by shunting the nominally 12.5 kΩ on-chip load resistor (see Figure 31) with 50 kΩ, adjusted by VR1. The calibration range is ±10% (18 mV/dB to 22 mV/dB), including full allowance for the variability in the value of the internal load.
PAGE 20
AD8307 Data Sheet APPLICATIONS INFORMATION VP, 2.7V TO 5.5V VR2 50kΩ RS INPUT –75dBm TO +16dBm 7 6 5 INP VPS ENB INT FOR VP = 3V, RS = 20kΩ VP = 5V, RS = 51kΩ INM COM OFS OUT 1 2 3 NC NC = NO CONNECT 4 OUTPUT 50mV/dB ±10% AD8031 AD8307 20mV/dB 32.
PAGE 21
Data Sheet AD8307 The front-end adaptation shown in Figure 41 provides the measurement of power being delivered from a transmitter final amplifier to an antenna. The range has been set to cover the power range −30 dBm (7.07 mV rms, or 1 μW) to +60 dBm (223 V rms, or 1 kW). A nominal voltage attenuation ratio of 158:1 (44 dB) is used; thus the intercept is moved from −84 dBm to −40 dBm and the AD8307, scaled 0.25 V/decade of power, now reads 1.5 V for a power level of 100 mW, 2.0 V at 10 W, and 2.
PAGE 22
AD8307 Data Sheet 2.50 2.25 VOUT (V) 2 1.50 1 1.25 0 1.00 –1 ERROR (WITH FILTER) 0.75 0.50 –2 01082-043 WITH FILTER 0.25 0 –100 –80 –60 –40 –20 INPUT LEVEL (dBm) 0 20 See Figure 40 for a more elaborate filter. To improve the law conformance at very low signal levels and at low frequencies, add C4 to the offset compensation loop. Figure 43.
PAGE 23
Data Sheet AD8307 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.
PAGE 24
AD8307 Data Sheet ORDERING GUIDE Model1 AD8307ANZ AD8307ARZ AD8307ARZ-REEL AD8307ARZ-RL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 13" Tape and Reel 8-Lead SOIC_N 7" Tape and Reel Z = RoHS Compliant Part. ©1997–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01082-0-12/19(F) Rev.