Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Custom amplification Log amplifier MSOP 8

0.1 GHz to 2.5 GHz 70 dB

Logarithmic Detector/Controller

Data Sheet

AD8313

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Wide bandwidth: 0.1 GHz to 2.5 GHz min

High dynamic range: 70 dB to ±3.0 dB

High accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz)

Fast response: 40 ns full-scale typical

Controller mode with error output

Scaling stable over supply and temperature

Wide supply range: 2.7 V to 5.5 V

Low power: 40 mW at 3 V

Power-down feature: 60 mW at 3 V

Complete and easy to use

APPLICATIONS

RF transmitter power amplifier setpoint control and level

monitoring

Logarithmic amplifier for RSSI measurement cellular base

stations, radio link, radar

FUNCTIONAL BLOCK DIAGRAM

+ +

AD8313

VOUT

VSET

COMM

PWDN

GAIN

BIAS

BAND GAP

REFERENCE

SLOPE

CONTROL

INTERCEPT

CONTROL

EIGHT 8dB 3.5GHz AMPLIFIER STAGES

8dB 8dB

VPOS

INHI

INLO

VPOS

8dB8dB

NINE DETECTOR CELLS

INT

I→V

V→

01085-C-001

Figure 1.

GENERAL DESCRIPTION

The AD8313 is a complete multistage demodulating logarithmic

amplifier that can accurately convert an RF signal at its input to

an equivalent decibel-scaled value at its dc output. The AD8313

maintains a high degree of log conformance for signal frequencies

from 0.1 GHz to 2.5 GHz. Application is straightforward,

requiring only a single supply of 2.7 V to 5.5 V and the addition

of a suitable input and supply decoupling. Operating on a 3 V

supply, its 13.7 mA consumption (for T

= 25°C) is only 41 mW.

A power-down feature is provided; the input is taken high to

initiate a low current (20 µA) sleep mode, with a threshold at

half the supply voltage.

The AD8313 is fabricated on Analog Devices, Inc., advanced

25 GHz silicon bipolar IC process and is available in an 8-lead

MSOP package. The operating temperature range is −40°C to

+85°C.

Table 1. Next Generation Upgrades for AD8313

Part Number Comments

ADL5513 Improved range and temperature stability,

operation up to 4 GHz

AD8318 Improved temperature stability, operation up

to 8 GHz

AD8317 Lower input range, improved temperature

stability, operation up to 10 GHz

AD8319 Lower input range, improved temperature

stability, operation up to 10 GHz

INPUT AMPLITUDE (dBm)

2.0

–80

OUTPUT VOLTAGE (V DC)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–70 –60 –50 –40 –30 –20 –10

FREQUENCY = 1.9GHz

–1

–2

–3

–

–5

OUTPUT ERROR (dB)

01085-C-002

Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude

Summary of content (24 pages)

PAGE 1
0.1 GHz to 2.5 GHz 70 dB Logarithmic Detector/Controller AD8313 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM + NINE DETECTOR CELLS + + + + I→V 8 VOUT 7 VSET 6 COMM 5 PWDN VPOS 1 CINT INHI 2 8dB 8dB 8dB LP 8dB INLO 3 V→I EIGHT 8dB 3.5GHz AMPLIFIER STAGES INTERCEPT CONTROL AD8313 VPOS 4 SLOPE CONTROL APPLICATIONS BAND GAP REFERENCE GAIN BIAS 01085-C-001 Wide bandwidth: 0.1 GHz to 2.5 GHz min High dynamic range: 70 dB to ±3.0 dB High accuracy: ±1.0 dB over 65 dB range (@ 1.
PAGE 2
AD8313 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Connections for Log (RSSI) Mode ................................ 15 Applications ....................................................................................... 1 Operating in Controller Mode ................................................. 15 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD8313 SPECIFICATIONS TA = 25°C, VS = 5 V1, RL = 10 kΩ, unless otherwise noted. Table 2. Parameter SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage Input Bias Currents Input Impedance LOG (RSSI) MODE 100 MHz5 ±3 dB Dynamic Range6 Range Center ±1 dB Dynamic Range Slope Intercept Test Conditions/Comments Min2 Typ Max2 Unit 2.5 VPOS – 0.75 10 900||1.1 GHz V µA Ω||pF4 65 −31.5 56 19 −88 dB dBm dB mV/dB dBm 0.
PAGE 4
AD8313 Parameter 2.5 GHz7 ±3 dB Dynamic Range Range Center ±1 dB Dynamic Range Slope Intercept Data Sheet Test Conditions/Comments Nominal conditions Min2 Typ 48 66 –34 46 20 –92 16 –111 Max2 Unit 25 –72 dB dBm dB mV/dB dBm 2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C ±3 dB Dynamic Range Range Center ±1 dB Dynamic Range Slope Intercept Temperature Sensitivity 3.
PAGE 5
Data Sheet Parameter POWER SUPPLY Operating Range Powered-Up Current Powered-Down Current AD8313 Test Conditions/Comments Min2 Typ 2.7 13.7 4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C 2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C 4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C 2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C 50 20 Max2 Unit 5.5 15.5 18.5 18.5 150 50 V mA mA mA µA µA Except where otherwise noted; performance at VS = 3 V is equivalent to 5 V operation.
PAGE 6
AD8313 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage VS VOUT, VSET, PWDN Input Power Differential (re: 50 Ω, 5.5 V) Input Power Single-Ended (re: 50 Ω, 5.5 V) Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V, VPOS 25 dBm 19 dBm 200 mW 200°C/W 125°C –40°C to +85°C –65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product.
PAGE 7
Data Sheet AD8313 VPOS 1 INHI 2 INLO 3 VPOS 4 AD8313 TOP VIEW (Not to Scale) 8 VOUT 7 VSET 6 COMM 5 PWDN 01085-C-003 PIN CONFIGURATION AND FUNCTION DESCRIPTION Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 4 2 3 5 6 7 8 Mnemonic VPOS INHI INLO PWDN COMM VSET VOUT Description Positive Supply Voltage (VPOS), 2.7 V to 5.5 V. Noninverting Input. This input should be ac-coupled. Inverting Input. This input should be ac-coupled.
PAGE 8
AD8313 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 5 1.8 1.8 4 1.6 1.6 3 1.4 1.4 2 100MHz 2.5GHz 1 –40°C 1.0 0 +25°C 0.8 0.8 0.6 0.6 –2 0.4 –3 900MHz 0.4 +85°C SLOPE AND INTERCEPT NORMALIZED AT +25°C AND APPLIED TO –40°C AND +85°C 0.2 0 –70 –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBm) –10 0 10 01085-C-004 0.2 0 –70 Figure 4. VOUT vs. Input Amplitude –60 –50 –40 –30 –20 –10 INPUT AMPLITUDE (dBm) –4 0 4 2.0 5 1.8 4 3 1.
PAGE 9
Data Sheet AD8313 –70 22 21 –80 INTERCEPT (dBm) SLOPE (mV/dB) +85°C 20 +25°C 19 –40°C 18 +85°C –90 +25°C –100 17 500 1000 1500 FREQUENCY (MHz) 2000 2500 –110 Figure 10. VOUT Slope vs. Frequency for Multiple Temperatures 0 500 1000 1500 FREQUENCY (MHz) 2500 2000 01085-C-013 0 01085-C-010 16 –40°C Figure 13. VOUT Intercept vs. Frequency for Multiple Temperatures –70 24 23 –75 SPECIFIED OPERATING RANGE SPECIFIED OPERATING RANGE 22 –80 INTERCEPT (dBm) SLOPE (mV/dB) 21 2.
PAGE 10
AD8313 Data Sheet 100.00 CH. 1 AND CH. 2: 200mV/DIV VS = +5.5V 13.7mA CH. 1 10.00 VS = +2.7V CH. 2 PULSED RF 100MHz, –45dBm CH. 1 GND 1.00 VPOS = +5V VPOS = +3V CH. 2 GND 0.10 40µA 0.01 0 1 2 3 PWDN VOLTAGE (V) 4 5 HORIZONTAL: 50ns/DIV 01085-C-016 20µA Figure 18. Response Time, No Signal to –45 dBm Figure 16. Typical Supply Current vs. PWDN Voltage CH. 1 AND CH. 2: 1V/DIV 01085-C-019 SUPPLY CURRENT (mA) AVERAGE: 50 SAMPLES CH. 1 & CH. 2: 500mV/DIV CH.
PAGE 11
Data Sheet AD8313 CIRCUIT DESCRIPTION capacity of the first detector cell, and occurs at approximately 0 dBm. The practical dynamic range is over 70 dB to the ±3 dB error points. However, some erosion of this range can occur at temperature and frequency extremes. Useful operation to over 3 GHz is possible, and the AD8313 remains serviceable at 10 MHz, needing only a small amount of additional ripple filtering. NINE DETECTOR CELLS + + + + I→V 8 2.
PAGE 12
AD8313 Data Sheet With Pins 7 and 8 connected (log amp mode), the output can be stated as With Pins 7 and 8 disconnected (controller mode), the output can be stated as VOUT = VSLOPE ( PIN + 100 dBm) where PIN is the input power stated in dBm when the source is directly terminated in 50 Ω.
PAGE 13
Data Sheet AD8313 INTERFACES For high frequency use, Figure 26 shows the input impedance plotted on a Smith chart. This measured result of a typical device includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground from the INLO pin. POWER-DOWN INTERFACE, PWDN VPOS 4 50kΩ 150kΩ 150kΩ COMM 6 01085-C-024 TO BIAS ENABLE 75kΩ PWDN 5 Figure 24.
PAGE 14
AD8313 Data Sheet SETPOINT INTERFACE, VSET VPOS 1 Rev. E | Page 14 of 24 FDBK TO O/P STAGE 25µA R1 12kΩ LP VSET 8 R2 6kΩ R3 1.5kΩ COMM 6 Figure 28. Setpoint Interface Circuitry 01085-C-028 The setpoint interface is shown in Figure 28. The voltage, VSET, is divided by a factor of 3 in a resistive attenuator of 18 kΩ total resistance. The signal is converted to a current by the action of the op amp and the resistor R3 (1.
PAGE 15
Data Sheet AD8313 APPLICATIONS INFORMATION BASIC CONNECTIONS FOR LOG (RSSI) MODE OPERATING IN CONTROLLER MODE Figure 29 shows the AD8313 connected in its basic measurement mode. A power supply between 2.7 V and 5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 µF surface-mount ceramic capacitor and a 10 Ω series resistor. Figure 30 shows the basic connections for operation in controller mode.
PAGE 16
AD8313 Data Sheet INPUT COUPLING 3 BALANCED The signal can be coupled to the AD8313 in a variety of ways. In all cases, there must not be a dc path from the input pins to ground. Some of the possibilities include dual-input coupling capacitors, a flux-linked transformer, a printed circuit balun, direct drive from a directional coupler, or a narrow-band impedance matching network. 2 Figure 32 shows a simple broadband resistive match. A termination resistor of 53.
PAGE 17
Data Sheet AD8313 Typically, the AD8313 needs to be matched to 50 Ω. The input impedance of the AD8313 at 100 MHz can be read from the Smith chart (Figure 26) and corresponds to a resistive input impedance of 900 Ω in parallel with a capacitance of 1.1 pF. To make the matching process simpler, the AD8313 input capacitance, CIN, can be temporarily removed from the calculation by adding a virtual shunt inductor (L2), which resonates away CIN (Figure 36).
PAGE 18
AD8313 Data Sheet Figure 37 shows the voltage response of the 100 MHz matching network. Note the high attenuation at lower frequencies typical of a high-pass network. R1 10 +VS 1 VPOS 0.1F VOUT 8 20mV/dB AD8313 2 INHI REXT VSET 7 15 4 VPOS PWDN 5 0.1F Figure 39. Adjusting the Log Slope to a Fixed Value 5 Table 6. Values for REXT in Figure 39 01085-C-037 0 –5 50 100 FREQUENCY (MHz) 200 Figure 37.
PAGE 19
Data Sheet AD8313 In Figure 41, an emitter-follower provides the current gain, when a 100 Ω load can readily be driven to full-scale output. While a high ß transistor such as the BC848BLT1 (min ß = 200) is recommended, a 2 kΩ pull-up resistor between VOUT and +VS can provide additional base current to the transistor. +VS R1 10 MIN = 200 1 0.1F VPOS VOUT 8 AD8313 2 INHI BC848BLT1 13k OUTPUT VSET 7 10k +VS 3 INLO 4 VPOS PWDN 5 R3 10 RL 100 COMM 6 0.1F 01085-C-041 +VS Figure 41.
PAGE 20
AD8313 Data Sheet EVALUATION BOARD SCHEMATIC AND LAYOUT Figure 44 shows the schematic of the AD8313 evaluation board. Note that uninstalled components are indicated as open. This board contains the AD8313 as well as the AD8009 currentfeedback operational amplifier. This is a 4-layer board (top and bottom signal layers, ground, and power). The top layer silkscreen and layout are shown in Figure 42 and Figure 43.
PAGE 21
AD8313 Figure 42. Layout of Signal Layer 01085-C-049 001085-C-048 Data Sheet Figure 43. Signal Layer Silkscreen Rev.
PAGE 22
AD8313 Data Sheet VNEG C7 0.1µF R4 0Ω R12 301Ω Z1 VPS1 C1 680pF C3 0.1µF INHI 1 VSET 7 R9 0Ω 3 INLO COMM 6 4 VPOS PWDN 5 C5 0.1µF R3 0Ω L/R 53.6Ω INLO R2 10Ω AD8009 R11 0Ω AD8313 C4 0.1µF R7 0Ω VOUT R6 OPEN C6 OPEN R8 20kΩ EXT VSET VPS2 R2 10Ω VPS1 R5 0Ω Z2 VOUT 8 INHI 2 C2 680pF VPOS TP1 EXT ENABLE SW1 B 01085-C-046 R1 10Ω R10 OPEN A Figure 44. Evaluation Board Schematic Table 8.
PAGE 23
Data Sheet AD8313 NOT CRITICAL DIMENSIONS 35 TRACE WIDTH 15.4 48 54.4 90.6 50 16 28 41 22 75 20 10 19 UNIT = MILS 50 20 27.5 51 91.3 48 126 51.7 01085-C-047 46 Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network Rev.
PAGE 24
AD8313 Data Sheet OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 46 .