Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Video editing Line driver, Transmitter QSOP 20

3.3 V Upstream

Cable Line Driver

Data Sheet

AD8324

Rev. B Document Feedback

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FEATURES

Supports DOCSIS 2.0 and EuroDOCSIS specifications for

reverse path transmission systems

Gain programmable in 1 dB steps over a 59 dB range

Low distortion at 61 dBmV output

−59 dBc SFDR at 21 MHz

−54 dBc SFDR at 65 MHz

Output noise level at minimum gain 1.3 nV/√Hz

Maintains 75 Ω output impedance in transmit-enable and

transmit-disable condition

Upper bandwidth of 100 MHz (full gain range)

3.3 V supply operation

Supports SPI® interfaces

APPLICATIONS

DOCSIS 2.0 and EuroDOCSIS cable modems

CATV set-top boxes

CATV telephony modems

Coaxial and twisted pair line drivers

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD8324 is a low cost amplifier designed for coaxial line

driving. The features and specifications make the AD8324

ideally suited for DOCSIS® 2.0

and EuroDOCSIS™ applications.

The gain of the AD8324 is digitally controlled. An 8-bit serial

word determines the desired output gain over a 59 dB range,

resulting in gain changes of 1 dB/LSB.

The AD8324 accepts a differential or single-ended input signal.

The output is specified for driving a 75 Ω load through a 1:1

transformer.

Distortion performance of –54 dBc is achieved with an output

level up to 61 dBmV at 65 MHz bandwidth.

This device has a sleep mode function that reduces the quiescent

current to 30 μA and a full power-down function that reduces

power-down current to 2.5 mA.

The AD8324 is packaged in a low cost, 20-lead LFCSP and a

20-lead QSOP. The AD8324 operates from a single 3.3 V supply.

Figure 2. Worst Harmonic Distortion vs. Frequency

DOCSIS is a registered trademark of Cable Television Laboratories, Inc.

IN+

IN–

OUT+

OUT–

(SINGLE) = 550Ω

(DIFF) = 1100Ω

RAMP

OUT

DIFF =

75Ω

SHIFT

DATA LATCH

DECODE

POWER-

DOWN LOGIC

GND DATEN SDATA

TXEN

SLEEP

AD8324

VERNIER

DIFF

OR SINGLE

INPUT

AMP

OUTPUT

STAGE

BYP

ATTENUATION

CORE

04339-0-001

FREQUENCY (MHz)

DISTORTION (dBc)

515

–80

–70

–50

–60

–40

25 35 45 55 65

04339-0-002

OUT

= 61dBmV @ DEC 60

SECOND HARMONIC

OUT

= 61dBmV @ DEC 60

THIRD HARMONIC

Summary of content (16 pages)

PAGE 1
3.3 V Upstream Cable Line Driver AD8324 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM BYP VIN+ VIN– VOUT+ DIFF OR SINGLE INPUT AMP ATTENUATION CORE VERNIER OUTPUT STAGE VOUT– ZIN (SINGLE) = 550Ω ZIN (DIFF) = 1100Ω 8 ZOUT DIFF = 75Ω DECODE 8 AD8324 POWERDOWN LOGIC RAMP DATA LATCH 8 SHIFT REGISTER 04339-0-001 Supports DOCSIS 2.
PAGE 2
AD8324 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Programming for the AD8324 ........................................ 12 Applications ....................................................................................... 1 Input Bias, Impedance, and Termination................................ 12 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD8324 SPECIFICATIONS TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized using a 1:1 transformer 1 at the device output. Table 1.
PAGE 4
AD8324 Parameter POWER SUPPLY Operating Range Quiescent Current OPERATING TEMPERATURE RANGE Data Sheet Test Conditions/Comments Maximum gain Minimum gain Transmit disable (TXEN = 0) SLEEP mode (power down) 20-lead LFCSP 20-lead QSOP Min Typ Max Unit 3.13 195 25 1 3.3 207 39 2.5 30 3.47 235 50 4 500 V mA mA mA µA +85 +70 °C °C –40 –25 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB at 10 MHz. Guaranteed by design and characterization to ±6 sigma for TA = 25°C.
PAGE 5
Data Sheet AD8324 TIMING REQUIREMENTS VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted. Table 3. Parameter Clock Pulse Width (tWH) Clock Period (tC) Setup Time SDATA vs. Clock (tDS) Setup Time DATEN vs. Clock (tES) Hold Time SDATA vs. Clock (tDH) Hold Time DATEN vs. Clock (tEH) Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF) Min 16.0 32.0 5.0 15.0 5.0 3.0 Typ Max 10 Unit ns ns ns ns ns ns ns Timing Diagrams tDS SDATA VALID DATA-WORD G1 MSB . . .
PAGE 6
AD8324 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage, VCC Input Voltage VIN+, VIN– DATEN, SDATA, CLK, SLEEP, TXEN Internal Power Dissipation Operating Temperature Range 20-Lead LFCSP 20-Lead QSOP Storage Temperature Range Lead Temperature (Soldering, 60 sec) Table 5. Rating 3.63 V 1.5 V p-p –0.5 V to +3.63 V 776 mW –40°C to +85°C –25°C to +70°C –65°C to +150°C 300°C Model 20-Lead QSOP 20-Lead LFCSP 1 2 θJA 83.21 30.
PAGE 7
Data Sheet AD8324 GND 1 15 RAMP GND 3 18 TXEN GND 2 AD8324 14 VOUT+ GND 4 17 RAMP VIN+ 3 13 VOUT– VIN– 4 TOP VIEW (Not to Scale) GND 5 16 VOUT+ TOP VIEW VIN– 6 (Not to Scale) 15 VOUT– GND 7 14 BYP VIN+ 5 12 BYP 11 NC 04339-0-006 10 SLEEP 9 GND 8 CLK 7 SDATA DATEN 6 AD8324 DATEN 8 13 NC SDATA 9 12 SLEEP CLK 10 11 GND NC = NO CONNECT NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
PAGE 8
AD8324 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –40 –40 VOUT = 62dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 –50 DISTORTION (dBc) VOUT = 62dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 –60 –60 VOUT = 60dBmV @ DEC 60 –70 04339-0-007 –70 VOUT = 60dBmV @ DEC 60 –80 5 15 25 35 45 FREQUENCY (MHz) 55 04339-0-010 DISTORTION (dBc) –50 –80 5 65 Figure 7. Second-Order Harmonic Distortion vs. Frequency for Various Output Powers 15 25 35 45 FREQUENCY (MHz) 55 65 Figure 10.
PAGE 9
Data Sheet AD8324 0 60 CH PWR 12dBm WORST ACP –61dBc VOUT = 57dBmV/TONE @ MAX GAIN 50 –20 40 –30 30 –40 20 VOUT (dBmV) –50 –60 –70 10 0 –10 CU1 C0 C0 –90 –20 CU1 04339-0-013 –80 CL1 CL1 –100 CENTER 21 MHz 100 kHz/DIV –30 –40 41.6 SPAN 1 MHz 41.7 41.8 41.9 42.0 42.1 42.2 FREQUENCY (MHz) 42.3 42.4 42.5 Figure 16. Two-Tone Intermodulation Distortion Figure 13. Adjacent Channel Power 0 40 TXEN = 0 VIN = 27.
PAGE 10
Data Sheet 110 160 BETWEEN BURST TRANSIENTS (mV p-p) f = 10MHz TXEN = 1 140 120 100 80 60 40 20 0 0 6 12 18 24 30 36 42 48 54 150 130 110 90 70 04339-0-020 QUIESCENT SUPPLY CURRENT (mA) 170 50 30 18 24 30 36 42 60 50 DOCSIS 2.0 BETWEEN BURST TRANSIENT SPECIFICATION 40 30 AD8324 20 10 6 12 18 24 30 36 42 48 54 Figure 21. Between Burst Transient vs. Gain Control TA = 25°C 12 70 GAIN CONTROL (Decimal Code) 210 6 80 0 Figure 19. Output Referred Voltage Noise vs.
PAGE 11
Data Sheet AD8324 TEST CIRCUIT 3.3V 0.1µF VCC VIN+ 39.5Ω 18.7Ω 1/2 VIN 1/2 VIN VOUT+ 1:1 75Ω AD8324 VIN– RL VOUT– BYP GND 0.1µF 0.1µF Figure 22. Typical Characterization Circuit Rev. B | Page 11 of 16 04339-0-022 18.
PAGE 12
AD8324 Data Sheet APPLICATIONS INFORMATION GENERAL APPLICATIONS The AD8324 is primarily intended for use as the upstream power amplifier (PA) in Data-Over-Cable Service Interface Specification (DOCSIS) certified cable modems and CATV set-top boxes. The upstream signal is either a quadrature phase shift keying (QPSK) or a quadrature amplitude modulation (QAM) signal generated by a digital signal processor (DSP), a dedicated QPSK/QAM modulator, or a digital-to-analog converter (DAC).
PAGE 13
Data Sheet AD8324 VCC 10µF AD8324-JRQ 1 2 0.1µF 3 VIN+ 4 5 ZIN = 150Ω 174Ω 6 7 8 VIN– 9 0.1µF 10 GND GND VCC VCC GND TXEN GND RAMP VIN+ VOUT+ VIN– VOUT– GND BYP DATEN NC SDATA SLEEP GND CLK 20 19 18 0.1µF 17 TO DIPLEXER ZIN = 75Ω 1:1 16 15 TOKO 458PT-1556 14 13 0.1µF 12 11 1kΩ DATEN 1kΩ SDATA 1kΩ CLK 04339-0-023 1kΩ TXEN 1kΩ SLEEP Figure 23. Typical Application Circuit Table 7.
PAGE 14
AD8324 Data Sheet The BYP pin (Pin 12/Pin 14) is used to decouple the output stage to ground. Typically, for normal DOCSIS operation, decouple the BYP pin to ground with a 0.1 µF capacitor. In applications that require transient on/off times faster than 2 µs, smaller capacitors can be used; however, note that the BYP pin must always be decoupled to ground.
PAGE 15
Data Sheet AD8324 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SOURCE Typical applications for the AD8324 use a differential input signal from a modulator or a DAC. Refer to Table 8 for common values of R4, or calculate other input configurations using the equation in Figure 24. This circuit configuration gives optimal distortion results due to the symmetric input signals. Note that this configuration is used to characterize the AD8324.
PAGE 16
AD8324 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BCS SQ 0.50 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD 5 10 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.23 0.18 SEATING PLANE 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-09-2012-B 0.75 0.60 0.