Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Custom amplification Variable V factor LFCSP-32-VQ

Ultralow Noise VGAs with

Preamplifier and Programmable R

AD8331/AD8332/AD8334

Rev. G

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Ultralow noise preamplifier (preamp)

Voltage noise = 0.74 nV/√Hz

Current noise = 2.5 pA/√Hz

3 dB bandwidth

AD8331: 120 MHz

AD8332, AD8334: 100 MHz

Low power

AD8331: 125 mW/channel

AD8332, AD8334: 145 mW/channel

Wide gain range with programmable postamp

−4.5 dB to +43.5 dB in LO gain mode

7.5 dB to 55.5 dB in HI gain mode

Low output-referred noise: 48 nV/√Hz typical

Active input impedance matching

Optimized for 10-bit/12-bit ADCs

Selectable output clamping level

Single 5 V supply operation

AD8332 and AD8334 available in lead frame chip scale package

APPLICATIONS

Ultrasound and sonar time-gain controls

High performance automatic gain control (AGC) systems

I/Q signal processing

High speed, dual ADC drivers

GENERAL DESCRIPTION

The AD8331/AD8332/AD8334 are single-, dual-, and quad-

channel, ultralow noise linear-in-dB, variable gain amplifiers

(VGAs). Optimized for ultrasound systems, they are usable as a

low noise variable gain element at frequencies up to 120 MHz.

Included in each channel are an ultralow noise preamp (LNA),

an X-AMP® VGA with 48 dB of gain range, and a selectable gain

postamp with adjustable output limiting. The LNA gain is 19 dB

with a single-ended input and differential outputs. Using a single

resistor, the LNA input impedance can be adjusted to match a

signal source without compromising noise performance.

The 48 dB gain range of the VGA makes these devices suitable

for a variety of applications. Excellent bandwidth uniformity is

maintained across the entire range. The gain control interface

provides precise linear-in-dB scaling of 50 dB/V for control

voltages between 40 mV and 1 V. Factory trim ensures excellent

part-to-part and channel-to-channel gain matching.

FUNCTIONAL BLOCK DIAGRAM

03199-001

VOL

VOH

MID

LNA

48dB

ATTENUATOR

ENB

INH

LMD

IPLOPLON

GAIN

AD8331/AD8332/AD8334

–

CLAMP

RCLMP

HIL

3.5dB OR 15.5dB

19dB

VCM

BIAS

VGA BIAS AND

INTERPOLATOR

GAIN

CONTROL

INTERFACE

21dB

Figure 1. Signal Path Block Diagram

–10

100k 1M 10M 100M 1G

GAIN (dB)

FREQUENCY (Hz)

03199-002

GAIN

= 1V

GAIN

= 0.8V

GAIN

= 0.6V

GAIN

= 0.4V

GAIN

= 0.2V

GAIN

= 0V

HI GAIN

MODE

Figure 2. Frequency Response vs. Gain

Differential signal paths result in superb second- and third-

order distortion performance and low crosstalk.

The low output-referred noise of the VGA is advantageous in

driving high speed differential ADCs. The gain of the postamp

can be pin selected to 3.5 dB or 15.5 dB to optimize gain range

and output noise for 12-bit or 10-bit converter applications. The

output can be limited to a user-selected clamping level, preventing

input overload to a subsequent ADC. An external resistor adjusts

the clamping level.

The operating temperature range is −40°C to +85°C. The

AD8331 is available in a 20-lead QSOP package, the AD8332 is

available in 28-lead TSSOP and 32-lead LFCSP packages, and

the AD8334 is available in a 64-lead LFCSP package.

Summary of content (56 pages)

PAGE 1
Ultralow Noise VGAs with Preamplifier and Programmable RIN AD8331/AD8332/AD8334 FEATURES Ultrasound and sonar time-gain controls High performance automatic gain control (AGC) systems I/Q signal processing High speed, dual ADC drivers GENERAL DESCRIPTION The AD8331/AD8332/AD8334 are single-, dual-, and quadchannel, ultralow noise linear-in-dB, variable gain amplifiers (VGAs). Optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 MHz.
PAGE 2
AD8331/AD8332/AD8334 TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound TGC Application ................................................... 34 Applications ....................................................................................... 1 High Density Quad Layout ....................................................... 34 General Description .........................................................................
PAGE 3
AD8331/AD8332/AD8334 4/08—Rev. E to Rev. F Changed RFB to RIZ Throughout ..................................................... 4 Changes to Figure 1........................................................................... 1 Changes to Table 1, LNA and VGA Characteristics, Output Offset Voltage, Conditions ............................................................... 4 Changes to Quiescent Current per Channel and Power Down Current Parameters ..............................................................
PAGE 4
AD8331/AD8332/AD8334 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating, −4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. Table 1.
PAGE 5
AD8331/AD8332/AD8334 Parameter Output Signal Range, Postamplifier Differential Output Offset Voltage AD8331 AD8332, AD8334 Output Short-Circuit Current Harmonic Distortion AD8331 HD2 HD3 HD2 HD3 AD8332, AD8334 HD2 HD3 HD2 HD3 Input 1 dB Compression Point Two-Tone Intermodulation Distortion (IMD3) AD8331 AD8332, AD8334 Output Third-Order Intercept AD8331 AD8332, AD8334 Channel-to-Channel Crosstalk (AD8332, AD8334) Overload Recovery Group Delay Variation ACCURACY Absolute Gain Error 2 Gain Law Conformance 3
PAGE 6
AD8331/AD8332/AD8334 Parameter ENABLE INTERFACE (PIN ENB, PIN ENBL, PIN ENBV) Logic Level to Enable Power Logic Level to Disable Power Input Resistance Power-Up Response Time HILO GAIN RANGE INTERFACE (PIN HILO) Logic Level to Select HI Gain Range Logic Level to Select LO Gain Range Input Resistance OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR LO GAIN) Accuracy HILO = LO HILO = HI MODE INTERFACE (PIN MODE) Logic Level for Positive Gain Slope Logic Level for Negative Gain Slope Input Resistance POWER SUPPLY (PI
PAGE 7
AD8331/AD8332/AD8334 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2.
PAGE 8
AD8331/AD8332/AD8334 20 COMM 19 ENBL 3 18 ENBV LON 4 17 COMM LOP 5 16 VOL COML 6 15 VOH VIP 7 14 VPOS VIN 8 13 HILO MODE 9 12 RCLMP GAIN 10 11 VCM LMD 1 INH 2 VPSL PIN 1 INDICATOR AD8331 TOP VIEW (Not to Scale) 03199-003 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. 20-Lead QSOP Pin Configuration (AD8331) Table 3. 20-Lead QSOP Pin Function Description (AD8331) Pin No.
PAGE 9
LMD1 4 LMD2 5 6 VIN2 8 21 VIN1 VCM2 9 20 VCM1 GAIN 10 19 HILO INH2 RCLMP 11 18 ENB VPS2 7 VOH2 12 17 VOH1 LON2 8 VOL2 13 16 VOL1 COMM 14 15 VPSV TOP VIEW (Not to Scale) 03199-004 7 ENBL ENBV 29 28 27 26 25 24 COMM 23 VOH1 22 VOL1 AD8332 21 VPSV TOP VIEW (Not to Scale) 20 NC 19 VOL2 18 VOH2 9 10 17 COMM 11 12 13 14 15 16 NC = NO CONNECT 03199-005 3 VIP2 AD8332 30 GAIN 2 INH1 6 31 PIN 1 INDICATOR RCLMP VIP1 VPS1 COM1 5 HILO
PAGE 10
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 COM2 COM1 INH1 LMD1 NC LON1 LOP1 VIP1 VIN1 VPS1 GAIN12 CLMP12 EN12 EN34 VCM1 VCM2 AD8331/AD8332/AD8334 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD8334 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COM12 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 MODE NC COM34 VOH3 VOL3 VPS34 VOL4 VOH4 COM34 NOTES 1.
PAGE 11
AD8331/AD8332/AD8334 Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic GAIN34 CLMP34 HILO VCM4 VCM3 NC COM34 VOH4 VOL4 VPS34 VOL3 VOH3 COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 VCM2 VCM1 EN34 EN12 CLMP12 GAIN12 VPS1 VIN1 VIP1 LOP1 LON1 NC LMD1 INH1 COM1 COM2 EPAD Description Gain Control Voltage for CH3 and CH4. Output Clamping Level Input for CH3 and CH4. Gain Select for Postamp 0 dB or 12 dB.
PAGE 12
AD8331/AD8332/AD8334 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating, −4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. 50 60 50 PERCENT OF UNITS (%) 30 20 10 HILO = LO 0 0 0.2 0.4 0.6 20 10 ASCENDING GAIN MODE DESCENDING GAIN MODE (WHERE AVAILABLE) 03199-007 –10 30 0.8 1.0 0 –0.5 1.
PAGE 13
AD8331/AD8332/AD8334 0 VGAIN = 1V 50 VGAIN = 0.8V 40 VGAIN = 0.6V 30 VGAIN = 0.4V 20 VGAIN = 0.2V VOUT = 1V p-p –20 VGAIN = 1.0V CROSSTALK (dB) GAIN (dB) 60 AD8332 VGAIN = 0.7V –40 AD8334 VGAIN = 0.4V –60 –80 10 VGAIN = 0V 03199-013 –10 100k 1M 10M 100M 03199-016 –100 0 –120 100k 500M 1M FREQUENCY (Hz) Figure 13. Frequency Response for Various Values of VGAIN, HILO = HI 50 VGAIN = 0.
PAGE 14
AD8331/AD8332/AD8334 50j 30 SAMPLE SIZE = 100 0.2V < VGAIN < 0.7V RIN = 50Ω, RIZ = 270Ω 25 RIN = 6kΩ, RIZ = ∞ f = 100kHz 20 0Ω 17Ω 15 10 RIN = 75Ω, RIZ = 412Ω 0 03199-019 5 49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3 50.4 RIN = 100Ω, RIZ = 549Ω 50.5 RIN = 200Ω, RIZ = 1.1kΩ –25j –100j 03199-022 GAIN SCALING FACTOR –50j Figure 19. Gain Scaling Factor Histogram 100 Figure 22. Smith Chart, S11 vs. Frequency, 0.
PAGE 15
AD8331/AD8332/AD8334 500 1.00 RS = 0, RIZ = ∞, 0.95 VGAIN = 1V, f = 10MHz 300 HI GAIN AD8332 AD8334 LO GAIN AD8331 200 100 0 0 0.2 0.4 0.6 0.8 0.90 0.85 0.80 0.75 0.70 0.65 0.60 03199-028 INPUT-REFERRED NOISE (nV/ Hz) 400 03199-025 0.55 0.50 –50 1.0 –30 –10 VGAIN (V) Figure 25. Output-Referred Noise vs. VGAIN 10 2.0 1.5 1.0 1M 90 10M 1 RS THERMAL NOISE ALONE 0.1 100M 1 10 100 1k SOURCE RESISTANCE (Ω) Figure 26. Short-Circuit, Input-Referred Noise vs.
PAGE 16
AD8331/AD8332/AD8334 35 PREAMP LIMITED –30 f = 10MHz, RS = 50Ω f = 10MHz, VOUT = 1V p-p 25 20 15 10 HILO HILO HILO HILO 5 0 0 0.1 = LO, RIN = 50Ω = LO, RIZ = ∞ = HI, RIN = 50Ω = HI, RIz = ∞ 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –50 –60 –70 HILO = HI, HD3 0 200 400 600 800 Figure 31. Noise Figure vs. VGAIN Figure 34. Harmonic Distortion vs.
PAGE 17
AD8331/AD8332/AD8334 0 0 VOUT = 1V p-p VOUT = 1V p-p COMPOSITE (f1 + f2) G = 30dB –10 –20 –30 HILO = LO, HD3 IMD3 (dBc) –40 HILO = LO, HD2 –60 –80 –50 –70 HILO = HI, HD3 HILO = HI, HD2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 –80 HILO = HI –90 1M 1.0 10M VGAIN (V) Figure 40. IMD3 vs. Frequency 0 40 10MHz HILO = HI VOUT = 1V p-p 35 –20 1MHz HILO = LO HILO = LO, HD3 –60 –80 HILO = HI, HD3 10MHz HILO = LO 25 1MHz HILO = HI 20 15 10 HILO = HI, HD2 –100 03199-038 5 0 0.
PAGE 18
AD8331/AD8332/AD8334 5.0 20mV 4.5 100 4.0 90 HILO = HI VOUT (V p-p) 3.5 HILO = LO 3.0 2.5 2.0 1.5 10 0 10ns 03199-046 03199-043 1.0 500mV 0.5 0 0 5 10 15 20 25 30 35 40 45 50 70 80 RCLMP (kΩ) Figure 43. Large Signal Pulse Response, G = 30 dB, HILO = HI or LO, Top: Input, Bottom: Output Voltage 2 4 CL = 0pF CL = 10pF CL = 22pF CL = 47pF G = 30dB 1 Figure 46. Clamp Level vs. RCLMP INPUT G = 40dB RCLMP = 48.1kΩ RCLMP = 16.5kΩ 3 2 INPUT VOUT (V) 0 0 RCLMP = 7.
PAGE 19
AD8331/AD8332/AD8334 1V 2V 100 90 10 1V 1ms 03199-052 100ns 03199-049 0 Figure 52. Enable Response, Large Signal, Top: VENB, Bottom: VOUT, VINH = 150 mV p-p Figure 49. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, VGAIN = 1 V VGA Output Shown Attenuated by 24 dB 0 VPS1, VGAIN = 0.5V 1V –10 100 –20 90 PSRR (dB) VPSV, VGAIN = 0.5V –30 –40 –50 VPS1, VGAIN = 0V 10 –60 –70 03199-053 100ns 03199-050 0 –80 100k 1M 10M 100M FREQUENCY (Hz) Figure 50.
PAGE 20
AD8331/AD8332/AD8334 TEST CIRCUITS dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels because a 50 Ω load is driven directly. The generator is removed when noise measurements are made.
PAGE 21
AD8331/AD8332/AD8334 NETWORK ANALYZER 50Ω 50Ω 18nF 10kΩ 0.1µF OR 1µF FB* 120nH INH IN 0.1µF OR 1µF 0.1µF 237Ω LNA 28Ω VGA 1:1 22pF LMD 0.1µF *FERRITE BEAD 237Ω 0.1µF OR 1µF 0.1µF 28Ω 03199-058 OUT Figure 58. Test Circuit—Group Delay vs. Frequency for Two Values of AC Coupling 18nF 270Ω NETWORK ANALYZER 0.1µF 50Ω OUT FB* 120nH 0.1µF INH 237Ω 28Ω DUT 1:1 50Ω 22pF LMD 03199-059 0.1µF 237Ω 0.1µF 28Ω *FERRITE BEAD Figure 59. Test Circuit—LNA Input Impedance vs.
PAGE 22
AD8331/AD8332/AD8334 SPECTRUM ANALYZER B A GAIN 0.1µF 49.9Ω DUT 0.1µF SIGNAL GENERATOR TO MEASURE GAIN DISCONNECT FOR NOISE MEASUREMENT 50Ω 1:1 22pF 1Ω 50Ω INH IN 0.1µF 03199-062 FERRITE BEAD 0.1µF 120nH LMD Figure 62. Test Circuit—Noise Figure 18nF SPECTRUM ANALYZER 270Ω AD8332 0.1µF LPF 1kΩ 1:1 50Ω –6dB IN 28Ω INH –6dB 0.1µF DUT 1kΩ 22pF 0.1µF SIGNAL GENERATOR 28Ω 0.1µF 03199-063 LMD 50Ω Figure 63. Test Circuit—Harmonic Distortion vs.
PAGE 23
AD8331/AD8332/AD8334 OSCILLOSCOPE 18nF 270Ω 0.1µF 0.1µF 50Ω IN 28Ω INH DUT 1:1 22pF 50Ω 237Ω 237Ω LMD 0.1µF 0.1µF 28Ω 03199-066 FB* 120nH *FERRITE BEAD Figure 66. Test Circuit—Pulse Response Measurements OSCILLOSCOPE 18nF 270Ω 0.1µF FB* 120nH 0.1µF DIFF PROBE 255Ω INH CH1 CH2 DUT 22pF LMD 0.1µF 255Ω 0.1µF 9.5dB 50Ω TO PIN GAIN OR PIN ENxx *FERRITE BEAD PULSE GENERATOR 03199-067 50Ω RF SIGNAL GENERATOR Figure 67.
PAGE 24
AD8331/AD8332/AD8334 THEORY OF OPERATION LON1 LOP1 VIP1 VIN1 EN12 OVERVIEW The AD8331/AD8332/AD8334 operate in the same way.
PAGE 25
AD8331/AD8332/AD8334 The linear-in-dB, gain control interface is trimmed for slope and absolute accuracy. The gain range is +48 dB, extending from −4.5 dB to +43.5 dB in LO gain and +7.5 dB to +55.5 dB in HI gain mode. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V. Equation 1 and Equation 2 are the expressions for gain. GAIN (dB) = 50 (dB/V) × VGAIN − 6.5 dB, (HILO = LO) (1) or GAIN (dB) = 50 (dB/V) × VGAIN + 5.
PAGE 26
AD8331/AD8332/AD8334 UNTERMINATED Active Impedance Matching The LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance, RIN, is given in Equation 5, where A is the singleended gain of 4.5, and 6 kΩ is the unterminated input impedance. VOUT + – RESISTIVE TERMINATION (5) RS CIZ is needed in series with RIZ because the dc levels at Pin LON and Pin INH are unequal.
PAGE 27
AD8331/AD8332/AD8334 The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 76 shows their relative NF performance.
PAGE 28
AD8331/AD8332/AD8334 VGA Noise Common-Mode Biasing In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in accordance with the quantization noise floor of the ADC.
PAGE 29
AD8331/AD8332/AD8334 5.0 Output Clamping RCLMP = ∞ 4.0 8.8kΩ 3.5 3.5kΩ The accuracy of the clamping levels is approximately ±5% in LO or HI mode. Figure 80 illustrates the output characteristics for a few values of RCLMP. Rev. G | Page 29 of 56 3.0 2.5 RCLMP = 1.86kΩ 2.0 3.5kΩ 1.5 8.8kΩ 1.0 0.5 0 –3 RCLMP = ∞ –2 –1 03199-080 Output clamping can be used for ADC input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V.
PAGE 30
AD8331/AD8332/AD8334 APPLICATIONS INFORMATION CLMD 0.1µF The LMD pin (connected to the bias circuitry) must be bypassed to ground and signal sourced to the INH pin, which is capacitively coupled using 2.2 nF to 0.1 μF capacitors (see Figure 81). 1 2 +5V The unterminated input impedance of the LNA is 6 kΩ. The user can synthesize any LNA input resistance between 50 Ω and 6 kΩ. RIZ is calculated according to Equation 6 or selected from Table 7. RIZ (Nearest STD 1% Value, Ω) 280 412 562 1.13 k 3.
PAGE 31
AD8331/AD8332/AD8334 Gain Input Optional Output Voltage Limiting The GAIN pin is common to both channels of the AD8332. The input impedance is nominally 10 MΩ, and a bypass capacitor from 100 pF to 1 nF is recommended. The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive.
PAGE 32
AD8331/AD8332/AD8334 with gains less than 40 dB. The exact values of these components can be selected empirically. An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent. When the ADC resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and to mitigate charge kickback from the ADC inputs.
PAGE 33
AD8331/AD8332/AD8334 ADG736 When selecting overload protection, the important parameters are forward and reverse voltages and trr (or τrr). The Infineon BAS40-04 series shown in Figure 88 has a τrr of 100 ps and a VF of 310 mV at 1 mA. Many variations of these specifications can be found in vendor catalogs. 1.
PAGE 34
AD8331/AD8332/AD8334 ULTRASOUND TGC APPLICATION HIGH DENSITY QUAD LAYOUT The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications because it provides the means for echo location of reflected ultrasound energy. The AD8334 is the ideal solution for applications with limited board space. Figure 94 represents four channels routed to and away from this very compact quad VGA.
PAGE 35
AD8331/AD8332/AD8334 S3 EIN2 TP5 AD8332ARU C50 0.1µF LMD1 28 2 +5V CFB2 18nF + C80 22pF RFB2 274Ω C41 0.1µF 3 C74 1nF L6 120nH FB +5VLNA 5 6 7 VCM1 VPS1 26 8 LON2 LON1 LOP2 LOP1 COM2 COM1 VIP2 VIP1 VIN2 VIN1 C48 0.1µF TP2 GAIN TP7 GND R3 (RCLMP) C78 1nF 9 10 VCM2 VCM1 VIN–B JP8 DC2H CFB1 18nF RFB1 274Ω 24 C42 0.1µF 23 C59 0.1µF 22 21 20 HILO 11 C69 0.1µF C43 0.1µF +5VGA HI GAIN JP10 LO GAIN 19 +5VGA C68 1nF R27 100Ω L19 SAT L17 SAT C54 0.
PAGE 36
AD8331/AD8332/AD8334 3 + 2 C22 0.1µF C31 0.1µF 1 L4 120nH FB IN OUT GND C30 0.1µF OUT TAB L3 120nH FB R5 33Ω VIN+_A L2 120nH FB 1 2 3 R6 33Ω R4 C18 1.5kΩ C17 1nF C33 0.1µF 10µF 6.3V + C40 0.1µF R12 1.5kΩ C35 0.1µF C1 0.1µF C36 0.1µF 4 5 6 C52 10nF TP9 C32 + 0.1µF VREF C34 10µF 6.3V C38 0.1µF 8 C12 10µF 6.3V 9 C57 10nF C39 10µF C37 0.1µF VIN–_B S2 EXT CLOCK VIN+_B 13 14 15 R7 33Ω 16 17 C20 0.1µF R16 5kΩ R17 49.9Ω C15 1nF C62 18pF R18 499Ω C63 0.
PAGE 37
AD8331/AD8332/AD8334 DATACLKA 1 OTR_A D11_A D10_A D9_A D7_A D6_A RP 9 8 7 3 6 4 5 5 8 6 7 7 3 6 8 4 5 1 2 22 × 4 RP 10 9 G1 A4 Y4 A5 Y5 A6 Y6 A7 A8 Y7 Y8 + C3 0.1µF C28 10µF 6.
PAGE 38
AD8331/AD8332/AD8334 CH2 LNA INPUT CH3 LNA INPUT CH1 LNA INPUT CH4 LNA INPUT 61 60 57 56 54 53 52 51 49 VCM2 50 NC COM34 VOH4 VOL4 VPS34 VOL3 VOH3 COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 VCM1 55 32 VCM3 58 31 EN34 30 VCM4 29 EN12 59 28 HILO 62 NC 63 INH4 64 27 CLMP12 CLMP34 1 LMD4 INH2 26 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC = NO CONNECT CH1 DIFFERENTIAL OUTPUT CH2 DIFFERENTIAL OUTPUT CH3 DIFFERENTIAL OUTPUT CH4 DIFFERENT
PAGE 39
AD8331/AD8332/AD8334 AD8331 EVALUATION BOARD GENERAL DESCRIPTION The AD8331 evaluation board is a platform for testing and evaluating the AD8331 variable gain amplifier (VGA). The board is provided completely assembled and tested; the user simply connects an input signal, VGAIN sources, and a 5 V power supply. The AD8331-EVALZ is lead free and RoHS compliant. Figure 95 is a photograph of the board.
PAGE 40
AD8331/AD8332/AD8334 AD8331 EVALUATION BOARD SCHEMATICS GND3 GND4 GND1 GND2 GND +5V + CINH 0.1µF L1 120nH FB PROBE 3 INPUT CLAMP DIODES CLMD 0.1µF D1 CFB 0.018µF RFB 274µF L2 120nH FB BAT64-04 +5V LON 3 C6 0.1µF ENB INH ENBV VPS 19 DISABLE 18 ENABLE VGA_EN DISABLE DUT 4 LON COMM LOP VOL 17 LO C2 R8 ENABLE LNA_EN AD8331ARQ C1 R4 20 +5V 2 CSH 22pF COMM LMD2 5 16 L3 120nH FB R44 100Ω LOP 6 C16 0.1µF COML VOH 15 7 VIP VPOS 14 VIN HILO 13 W6 C26 0.
PAGE 41
AD8331/AD8332/AD8334 4395A ANALYZER GN D 1103 TEKPROBE POWER SUPPLY E3631A POWER SUPPLY +5V GND INSERT JUMPERS W5 AND W6 TO USE OUTPUT TRANSFORMER AND VOH SMA Figure 97. AD8331 Typical Board Test Connections Rev.
PAGE 42
AD8331/AD8332/AD8334 03199-118 03199-201 AD8331 EVALUATION BOARD PCB LAYERS Figure 98. AD8331-EVALZ Assembly 03199-202 03199-199 Figure 101. Internal Layer Ground Figure 99. Primary Side Copper 03199-200 03199-119 Figure 102. Power Plane Figure 103. Top Silkscreen Figure 100. Secondary Side Copper Rev.
PAGE 43
AD8331/AD8332/AD8334 AD8332 EVALUATION BOARD GENERAL DESCRIPTION The AD8332-EVALZ is a platform for the testing and evaluation of the AD8332 variable gain amplifier (VGA). The board is shipped assembled and tested, and users need only connect the signal and VGAIN sources to a single 5 V power supply. Figure 104 is a photograph of the component side of the board, and Figure 105 shows the schematic. The AD8332-EVALZ is lead free and RoHS compliant. Table 11.
PAGE 44
AD8331/AD8332/AD8334 EVALUATION BOARD SCHEMATICS C25 10µF GND GND1 GND2 GND3 GND4 + 1 C2 0.1µF C4 0.1µF L1 120nH FB LNA2 CSH2 22pF 2 INH2 LMD1 INH1 28 C1 0.1µF CFB1 18nF 3 +5V +5VLNA C6 0.1µF RFB2 274Ω C9 C3 0.1µF CSH1 22pF 27 CFB2 18nF CAL2 L8 120nH FB S6 LON2 LMD2 VPS2 VPS1 4 LON2 LON1 +5VLNA C7 0.1µF RFB1 274Ω C23 25 W8 5 LOP2 LOP1 W9 24 C5 C24 R12 6 C16 0.1µF COM2 COM1 C13 0.1µF 8 C10 0.
PAGE 45
AD8331/AD8332/AD8334 NETWORK ANALYZER 1103 TEKPROBE POWER SUPPLY VGAIN SUPPLY 03199-120 DIFFERENTIAL PROBE Figure 106. AD8332 Typical Board Test Connections Rev.
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AD8331/AD8332/AD8334 03199-121 03199-101 AD8332 EVALUATION BOARD PCB LAYERS Figure 107. AD8332-EVALZ Assembly 03199-102 03199-099 Figure 110. Ground Plane Figure 108. Primary Side Copper 03199-103 03199-100 Figure 111. Power Plane Figure 109. Secondary Side Copper Figure 112. Component Side Silkscreen Rev.
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AD8331/AD8332/AD8334 AD8334 EVALUATION BOARD GENERAL DESCRIPTION 03199-122 The AD8334-EVALZ is a platform for the testing and evaluation of the AD8334 variable gain amplifier (VGA). The board is shipped assembled and tested, and users need only connect the signal and VGAIN sources and a single 5 V power supply. Figure 113 is a photograph of the board. The AD8334-EVALZ is lead free and RoHS compliant. Figure 113. AD8334-EVALZ Top View Rev.
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AD8331/AD8332/AD8334 CONFIGURING THE INPUT IMPEDANCE Viewing Signals The board is built and tested using the components shown in black in Figure 115. Provisions are made for optional components (shown in gray) that can be installed at user discretion. As shipped, the input impedances of the low noise amplifiers (LNAs) are configured for 50 Ω to match the output impedances of most signal generators and network analyzers.
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AD8331/AD8332/AD8334 EVALUATION BOARD SCHEMATICS INH1 +5V 1 6 7 C69 0.1 µF 8 L3 +5V 120 nH 9 3 C53 0.1 µ F C L M P12 C67 0.1 µF C82 1 nF AD8334 VPS2 NC VIN3 VOH3 VOL3 LO N3 VPS34 NC VOL4 LMD3 17 18 19 21 22 23 C4 0.1 µF C12 22 pF CR3 20 C11 0.1 µF 1 2 25 26 C31 0.1 µF RFB4 CFB4 274Ω 18 nF 27 28 VC M3 VC M4 H IL O 30 C32 0.1 µF 31 L8 1 R22 120 nH R23 1 LO4 46 1 CLMP34 R50 4.
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AD8331/AD8332/AD8334 PROBE POWER SUPPLY PRECISION VOLTAGE REFERENCE (FOR VGAIN) GAIN CONTROL VOLTAGE GND NETWORK ANALYZER +5V DIFFERENTIAL PROBE POWER SUPPLY SIGNAL INPUT 03199-125 GND Figure 116. AD8334 Typical Board Test Connections (One Channel Shown) Rev.
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AD8331/AD8332/AD8334 03199-126 03199-128 AD8334 EVALUATION BOARD PCB LAYERS Figure 119. AD8334-EVALZ Inner Layer 1Copper Figure 118. AD8334-EVALZ Secondary Side Copper 03199-129 03199-127 Figure 117. AD8334-EVALZ Primary Side Copper Figure 120. AD8334-EVALZ Inner Layer 2 Copper Rev.
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03199-130 AD8331/AD8332/AD8334 Figure 121. AD8334-EVALZ Component Side Silkscreen Rev.
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AD8331/AD8332/AD8334 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 6.40 BSC 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 SEATING PLANE 8° 0° 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 122. 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) Dimensions shown in millimeters 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 1 10 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.025 (0.
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AD8331/AD8332/AD8334 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 32 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 17 16 9 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 8 0.25 MIN 0.80 MAX 0.65 TYP 12° MAX 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) COPLANARITY 0.08 0.
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AD8331/AD8332/AD8334 ORDERING GUIDE Model 1 AD8331ARQ AD8331ARQ-REEL AD8331ARQ-REEL7 AD8331ARQZ AD8331ARQZ-RL AD8331ARQZ-R7 AD8331-EVALZ AD8332ACP-R2 AD8332ACP-REEL AD8332ACP-REEL7 AD8332ACPZ-R2 AD8332ACPZ-R7 AD8332ACPZ-RL AD8332ARU AD8332ARU-REEL AD8332ARU-REEL7 AD8332ARUZ AD8332ARUZ-R7 AD8332ARUZ-RL AD8332-EVALZ AD8334ACPZ AD8334ACPZ-REEL AD8334ACPZ-REEL7 AD8334-EVALZ 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°