Datasheet

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Ultralow Distortion IF VGA

Data Sheet

AD8375

Rev. A

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FEATURES

Bandwidth of 630 MHz (−3 dB)

Gain range: −4 dB to +20 dB

Step size: 1 dB ± 0.2 dB

Differential input and output

Noise figure: 8 dB @ maximum gain

Output IP3 of ~50 dBm at 200 MHz

Output P1dB of 19 dBm at 200 MHz

Provides constant SFDR vs. gain

Parallel 5-bit control interface

Power-down feature

Single 5 V supply operation

24-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Differential ADC drivers

High IF sampling receivers

Wideband multichannel receivers

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

A2A3A4 A1 A0

POST-AMP

REGISTERS

AND

GAIN DECODER

VPOS

COMM

AD8375

VCOM

VIN+

VIN–

PWUP

OUT+

OUT–

06724-001

Figure 1.

GENERAL DESCRIPTION

The AD8375 is a digitally controlled, variable gain, wide

bandwidth amplifier that provides precise gain control, high

IP3, and low noise figure. The excellent distortion performance

and high signal bandwidth make the AD8375 an excellent gain

control device for a variety of receiver applications.

Using an advanced high speed SiGe process and incorporating

proprietary distortion cancellation techniques, the AD8375

achieves 50 dBm output IP3 at 200 MHz.

The AD8375 provides a broad 24 dB gain range with 1 dB

resolution. The gain is adjusted through a 5-pin control interface

and can be driven using standard TTL levels. The open-collector

outputs provide a flexible interface, allowing the overall signal

gain to be set by the loading impedance. Thus, the signal

voltage gain is directly proportional to the load.

The AD8375 is powered on by applying the appropriate logic

level to the PWUP pin. The quiescent current of the AD8375 is

typically 130 mA. When powered down, the AD8375 consumes

less than 5 mA and offers excellent input-to-output isolation.

Fabricated on an Analog Devices, Inc., high speed SiGe process,

the AD8375 is supplied in a compact, thermally enhanced,

4 mm × 4 mm, 24-lead LFCSP package and operates over the

temperature range of −40°C to +85°C.

–40

–60

–50

–70

–90

–80

–100

–110

HARMONIC DISTORTION (dBc), OUTPUT @ 2V p-p

OIP3 (dBm), OUTPUT @ 3dBm/TONE

40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

06724-052

OIP3

HD2

HD3

Figure 2. Harmonic Distortion and Output IP3 vs. Frequency

Summary of content (24 pages)

PAGE 1
Ultralow Distortion IF VGA AD8375 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Bandwidth of 630 MHz (−3 dB) Gain range: −4 dB to +20 dB Step size: 1 dB ± 0.2 dB Differential input and output Noise figure: 8 dB @ maximum gain Output IP3 of ~50 dBm at 200 MHz Output P1dB of 19 dBm at 200 MHz Provides constant SFDR vs.
PAGE 2
AD8375 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure ............................................................................ 12 Applications ....................................................................................... 1 Applications..................................................................................... 13 Functional Block Diagram .......................................
PAGE 3
Data Sheet AD8375 SPECIFICATIONS VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, unless otherwise noted. Table 1.
PAGE 4
AD8375 Data Sheet Parameter POWER INTERFACE Supply Voltage VPOS and Output Quiescent Current vs. Temperature Power-Down Current vs. Temperature POWER-UP/GAIN CONTROL VIH VIL Logic Input Bias Current Conditions Thermal connection made to exposed paddle under device −40°C ≤ TA ≤ +85°C PWUP low −40°C ≤TA ≤ +85°C Pin A0 to Pin A4, Pin PWUP Minimum voltage for a logic high Maximum voltage for a logic low Min Typ Max Unit 4.5 120 5.0 125 5.5 130 150 V mA mA mA mA 2.5 3 1.6 0.8 900 Table 2.
PAGE 5
Data Sheet AD8375 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage, VPOS PWUP, A0 to A4 Input Voltage, VIN+, VIN− DC Common Mode VCOM Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V −0.6 V to (VPOS + 0.6 V) −0.15 V to +4.15 V VCOM ± 0.25 V ±6 mA 825 mW 63.6°C/W 14.
PAGE 6
AD8375 Data Sheet 24 23 22 21 20 19 COMM VPOS COMM COMM COMM PWUP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR AD8375 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VOUT– VOUT+ VOUT– VOUT+ COMM VPOS NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND. SOLDER TO A LOW IMPEDANCE GROUND PLANE. 06724-002 A1 A0 VPOS VPOS COMM VPOS 7 8 9 10 11 12 VCOM VIN+ VIN– A4 A3 A2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 7
Data Sheet AD8375 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted. 25 20 1.0 46MHz 70MHz 140MHz 200MHz 0.8 0.6 GAIN ERROR (dB) GAIN (dB) 15 10 5 0.4 0.2 0 –0.2 –0.4 0 –0.6 –5 15 00101 20 00000 –1.0 –4 11000 Figure 4. Gain vs.
PAGE 8
AD8375 Data Sheet 55 AV = +20dB 51 50 50 AV = +10dB AV = 0dB 49 60 AV = 20dB 45 OIP3 (dBm) 48 OIP3 (dBm) 65 +25°C 20dB –40°C 20dB +85°C 20dB +25°C 0dB –40°C 0dB +85°C 0dB 47 46 AV = –4dB 45 55 40 50 AV = 0dB 44 35 45 30 40 OIP3 (dBm) 52 43 42 50 70 90 110 130 150 FREQUENCY (MHz) 170 190 210 25 –3 35 –2 –1 0 1 2 3 4 06724-012 40 30 06724-009 41 5 POUT PER TONE (dBm) Figure 10. Output Third-Order Intercept at Four Gains, Output Level at 3 dBm/Tone Figure 13.
PAGE 9
Data Sheet AD8375 –75 –80 –95 –85 –100 –90 –105 –95 –110 –100 –115 40 60 80 100 120 140 FREQUENCY (MHz) 160 –105 200 180 –95 –105 –115 –125 –5 –100 –85 HD3 +20dB HD3 +10dB HD3 0dB HD3 –4dB –95 –100 –120 –105 –2 –2 –1 0 1 2 3 4 5 –1 0 1 POUT (dBm) 2 3 4 5 –110 25 20 15 46MHz 70MHz 140MHz 200MHz 10 5 0 –4 –2 0 2 4 6 8 10 GAIN (dB) 12 14 16 18 20 Figure 20. NF vs.
PAGE 10
AD8375 Data Sheet REF3 POSITION –600mV/DIV REF3 SCALE 500mV 0pF 10pF EACH SIDE INPUT 2 R1 R3 M10.0ns 10.0GS/s IT 10.0ps/pt A CH1 960mV M2.5ns 20.0GS/s IT 10.0ps/pt A CH4 28.0mV REF3 500mV 2.5ns Figure 22. Gain Step Time Domain Response 06724-024 CH1 500mV Ω CH2 500mV Ω 06724-021 1 Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB OUTPUT REF1 POSITION –1.02/DIV REF1 SCALE 50mV RISE (C2) 1.384ns FALL(C2) 1.39ns INPUT 2 2 REF1 CH2 500mV REF1 50.0mV Figure 23.
PAGE 11
Data Sheet AD8375 0 1.00E–09 9.00E–10 –20 8.00E–10 DELAY (Seconds) S12 (dB) –40 –60 –80 +20dB +10dB 0dB –4dB 7.00E–10 6.00E–10 5.00E–10 4.00E–10 3.00E–10 2.00E–10 –100 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000 0.00E+00 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000 Figure 30. Group Delay vs. Frequency at Gain Figure 28. Reverse Isolation vs.
PAGE 12
AD8375 Data Sheet CIRCUIT DESCRIPTION BASIC STRUCTURE The dependency of the gain on the load is due to the opencollector architecture of the output stage. The AD8375 is a differential variable gain amplifier consisting of a 150 Ω digitally controlled passive attenuator followed by a highly linear transconductance amplifier. The dc current to the outputs of the amplifier is supplied through two external chokes.
PAGE 13
Data Sheet AD8375 APPLICATIONS BASIC CONNECTIONS +5V VCM Figure 35 shows the basic connections for operating the AD8375. A voltage between 4.5 V and 5.5 V should be applied to the supply pins. Each supply pin should be decoupled with at least one low inductance, surface-mount ceramic capacitor of 0.1 μF placed as close as possible to the device. 0.1µF 150Ω 1µH 0.1µF 50Ω AD8375 0.1µF AC 1µH 0.1µF 0.1µF 150Ω 37.
PAGE 14
AD8375 Data Sheet BROADBAND OPERATION For example, in the extreme case where the load is assumed to be high impedance, RL = ∞, the equation for R1 reduces to R1 = 75 Ω. Using the equation for VR, the applied voltage should be VR = 8 V. The measured single-tone low frequency harmonic distortion for a 2 V p-p output using 75 Ω resistive pull-ups is provided in Figure 37. The AD8375 uses an open-collector output structure that requires dc bias through an external bias network.
PAGE 15
Data Sheet AD8375 The addition of the series inductors L (series) in Figure 38 extends the bandwidth of the system and provides response flatness. Using 100 nH inductors as L (series), the wideband system response of Figure 40 is obtained. The wideband frequency response is an advantage in broadband applications such as predistortion receiver designs and instrumentation applications.
PAGE 16
AD8375 Data Sheet at dc, which introduces a zero into the transfer function. In addition, the ac coupling capacitors and the bias chokes introduce additional zeros into the transfer function. The final overall frequency response takes on a band-pass characteristic, helping to reject noise outside of the intended Nyquist zone. Table 5 provides initial suggestions for prototyping purposes. Some empirical optimization may be needed to help compensate for actual PCB parasitics.
PAGE 17
Data Sheet AD8375 LAYOUT CONSIDERATIONS +9V There are two output pins for each polarity, and they are oriented in an alternating fashion. When designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. A good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance. 96Ω TC3-1T 0.1µF 0.1µF 330Ω 25Ω 50Ω AD8375 T1 50Ω 96Ω AC 0.
PAGE 18
AD8375 Data Sheet EVALUATION BOARD Figure 46 shows the schematic of the AD8375 evaluation board. The silkscreen and layout of the component and circuit sides are shown in Figure 47 through Figure 50. The board is powered by a single supply in the 4.5 V to 5.5 V range. The power supply is decoupled by 10 µF and 0.1 µF capacitors at each power supply pin. Additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added.
PAGE 19
INN INP R2 0Ω R1 TC3-1T+ Figure 46. AD8375 Evaluation Board Schematic Rev. A | Page 19 of 24 VPOS C20 10µF C60 0.1µF T1 WA4 R72 R71 R70 C1 0.1µF WA3 R10 C2 0Ω 0.1µF R9 0Ω WA2 C11 0.1µF 23 22 21 20 C5 19 WA1 WA0 VPOS 13 C14 0.1µF VPOS VPOS VPOS COMM VPOS 9 10 11 12 6 A2 A0 8 COMM 14 5 A3 VOUT– 16 VOUT+ 15 AD8375 VOUT+ 17 VOUT– 18 4 A4 A1 7 3 VIN– 2 VIN+ 1 VCOM C63 0.1µF R13 0Ω COMM VPOS COMM COMM COMM PWUP 24 VPOS PU C13 0.1µF L2 1µH R16 0Ω VXA R19 C7 0.
PAGE 20
AD8375 Data Sheet Table 6. Evaluation Board Configuration Options Components C13, C14, C20, C63, C64, R91 Function Power Supply Decoupling. Nominal supply decoupling consists a 10 µF capacitor to ground followed by 0.1 µF capacitors to ground positioned as close to the device as possible. T1, C1, C2, C60, R1, R2, R9, R10, R70 to R72 Input Interface. T1 is a 3:1 impedance ratio balun to transform a 50 Ω singleended input into a 150 Ω balanced differential signal.
PAGE 21
AD8375 06724-048 06724-050 Data Sheet 06724-049 06724-051 Figure 49. Component Side Layout Figure 47. Component Side Silkscreen Figure 50. Circuit Side Layout Figure 48. Circuit Side Silkscreen Rev.
PAGE 22
AD8375 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 3.75 BSC SQ 1 0.50 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD 6 13 TOP VIEW 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 7 12 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 23
Data Sheet AD8375 NOTES Rev.