Datasheet

AD844
REV. C
–10–
Driving Large Capacitive Loads
Capacitive drive capability is 100 pF without an external net-
work. With the addition of the network shown in Figure 31, the
capacitive drive can be extended to over 10,000 pF, limited by
internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current
limit. Since this is roughly ±100 mA, under these conditions,
the maximum slew rate into a 1000 pF load is ±100 V/µs. Fig-
ure 32 shows the transient response of an inverting amplifier
(R1 = R2 = 1 kΩ) using the feed forward network shown in
Figure 31, driving a load of 1000 pF.
Figure 31. Feed Forward Network for Large Capacitive
Loads
Figure 32. Driving 1000 pF C
L
with Feed Forward Network
of Figure 31
Settling Time
Settling time is measured with the circuit of Figure 33. This cir-
cuit employs a false summing node, clamped by the two
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ,
and R
L
= 500 Ω. For the gain of –10, R5 = 50 Ω, R6 = 500 Ω
and R
L
was not used since the summing network loads the out-
put with approximately 275 Ω. Using this network in a unity-
gain configuration, settling time is 100 ns to 0.1% for a –5 V to
+5 V step with C
L
= 10 pF.
Figure 33. Settling Time Test Fixture
DC Error Calculation
Figure 34 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, I
BN
, flows in the
feedback resistor. I
BP
, the noninverting input bias current, flows
in the resistance at Pin 3 (R
P
), and the resulting voltage (plus
any offset voltage) will appear at the inverting input. The total
error, V
O
, at the output is:
V
O
= (I
BP
R
P
+V
OS
+ I
BN
R
IN
)1+
R1
R2






+I
BN
R1
Since I
BN
and I
BP
are unrelated both in sign and magnitude, in-
serting a resistor in series with the noninverting input will not
necessarily reduce dc error and may actually increase it.
Figure 34. Offset Voltage and Noise Model for the AD844
Noise
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are Inn, Inp, Vn, and the
amplifier induced noise at the output, V
ON
, is:
V
ON
= ((Inp R
P
)
2
+Vn
2
)1+
R1
R2






2
+(Inn R1)
2
Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, R1 = R2 = 1k, R
P
= 0, Vn =
2 nV/√
Hz, Inp = 10 pA/√Hz, Inn = 12 pA/√Hz, V
ON
calculates
to 12 nV/√
Hz. The current noise is dominant in this case, as it
will be in most low gain applications.