Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Op-amp Scrambler (zero drift) LFCSP 16 VQ (4x4)

AD8555

Rev. A | Page 20 of 28

04598-0-003

CODE

01001 1

WAVEFORM

Figure 51. Timing Diagram for Code 010011

Table 10. Timing Specifications

Timing Parameter Description Specification

Pulse Width for Loading 0 into Shift Register Between 50 ns and 10 μs

Pulse Width for Loading 1 into Shift Register ≥50 μs

Width between Pulses ≥10 μs

Table 11. 38-Bit Serial Word Format

Field No. Bits Description

Field 0 Bits 0 to 11 12-Bit Start of Packet 1000 0000 0001

Field 1 Bits 12 to 13 2-Bit Function

00: Change Sense Current

01: Simulate Parameter Value

10: Program Parameter Value

11: Read Parameter Value

Field 2 Bits 14 to 15 2-Bit Parameter

00: Second Stage Gain Code

01: First Stage Gain Code

10: Output Offset Code

11: Other Functions

Field 3 Bits 16 to 17 2-Bit Dummy 10

Field 4 Bits 18 to 25 8-Bit Value

Parameter 00 (Second Stage Gain Code): 3 LSBs Used

Parameter 01 (First Stage Gain Code): 7 LSBs Used

Parameter 10 (Output Offset Code): All 8 Bits Used

Parameter 11 (Other Functions)

Bit 0 (LSB): Master Fuse

Bit 1: Fuse for Production Test at Analog Devices

Bit 2: Parity Fuse

Field 5 Bits 26 to 37 12-Bit End of Packet 0111 1111 1110

A 38-bit serial word is used, divided into 6 fields. Assuming

each bit can be loaded in 60 μs, the 38-bit serial word transfers

in 2.3 ms. Table 11 summarizes the word format.

Fields 0 and 5 are the start of packet and end of packet field,

respectively. Matching the start of packet field with 1000 0000

0001 and the end of packet field with 0111 1111 1110 ensures

that the serial word is valid and enables decoding of the other

fields. Field 3 breaks up the data and ensures that no data com-

bination can inadvertently trigger the start of packet and end of

packet fields. Field 0 should be written first and Field 5 written

last. Within each field, the MSB must be written first and the

LSB written last. The shift register features power-on reset to

minimize the risk of inadvertent programming; power-on reset

occurs when VDD is between 0.7 V and 2.2 V.