Datasheet

AD8555
Rev. A | Page 8 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VSS 8
VOUT 7
VCLAMP 6
VPOS
5
VDD 1
FILT/DIGOUT 2
DIGIN 3
VNEG
4
AD8555
TOP VIEW
(Not to Scale)
04598-0-049
Figure 2. 8-Lead SOIC (Not Drawn to Scale)
04598-0-050
12
11
10
9
NC
VCLAMP
NC
VOUT
1 NC
2
3
5
NC
VNEG
NC
VPOS
6 7 8
4 DIGIN
NC
FILT/DIGOUT
16 15 14 13
AD8555
TOP VIEW
PIN 1
INDICATOR
AVDD DVDD AVSS DVSS
NOTES
1. NC = NO CONNE
C
T.
2
. THE EXPOSED PAD MUST BE CONNECTED
TO AVSS (PIN 14).
Figure 3. 16-Lead LFCSP (Not Drawn to Scale)
Table 5. Pin Configuration
SOIC LFCSP
Pin No. Mnemonic Pin No. Mnemonic Description
N/A 0 EPAD Exposed Pad. The exposed pad must be connected to AVSS (Pin 14)
1 VDD N/A N/A Positive Supply Voltage.
2 FILT/DIGOUT 2 FILTDIGOUT
Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor
between FILT and VDD or VSS implements a low-pass filtering function. In
read mode, this pin functions as a digital output.
3 DIGIN 4 DIGIN Digital Input.
4 VNEG 6 VNEG Negative Amplifier Input (Inverting Input).
5 VPOS 8 VPOS Positive Amplifier Input (Noninverting Input).
6 VCLAMP 10 VCLAMP Set Clamp Voltage at Output.
7 VOUT 12 VOUT
Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT
pin. In read mode, VOUT is a buffered digital output.
8 VSS N/A N/A Negative Supply Voltage.
N/A N/A 13, 14 DVSS, AVSS Negative Supply Voltage.
N/A N/A 15, 16 DVDD, AVDD Positive Supply Voltage.
N/A N/A 1, 3, 5, 7, 9, 11 NC Do Not Connect.