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Low Power, 14-Bit, 180 MSPS, Digital-to-Analog

Converter and Waveform Generator

Data Sheet

AD9102

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700 www.analog.com

FEATURES

On-chip 4096 × 14-bit pattern memory

On-chip DDS

Power dissipation @ 3.3 V, 4 mA output

96.54 mW @ 180 MSPS

Sleep mode: <5 mW @ 3.3 V

Supply voltage: 1.8 V to 3.3 V

SFDR to Nyquist

87 dBc @ 10 MHz output

Phase noise @ 1 kHz offset, 180 MSPS, 8 mA: −150 dBc/Hz

Differential current outputs: 8 mA max @ 3.3 V

Small footprint, 32-lead, 5 mm × 5 mm LFCSP with 3.6 mm ×

3.6 mm exposed paddle, and Pb-free package

APPLICATIONS

Medical instrumentation

Portable instrumentation

Signal generators, arbitrary waveform generators

Automotive radar

GENERAL DESCRIPTION

The AD9102 TxDAC® and waveform generator is a high perfor-

mance digital-to-analog converter (DAC) integrating on-chip

pattern memory for complex waveform generation with a direct

digital synthesizer (DDS).

The DDS is a 14-bit output, up to 180 MSPS master clock sine

wave generator with a 24-bit tuning word, allowing 10.8 Hz/LSB

frequency resolution.

SRAM data can include directly generated stored waveforms,

amplitude modulation patterns applied to DDS outputs, or DDS

frequency tuning words.

An internal pattern control state machine lets the user program

the pattern period for the DAC as well the start delay within the

pattern period for the signal output on the DAC .

A SPI interface is used to configure the digital waveform

generator and load patterns into the SRAM.

A gain adjustment factor and an offset adjustment are applied to

the digital signal on their way into the DAC.

The AD9102 offers exceptional ac and dc performance and

supports DAC sampling rates of up to 180 MSPS.

The flexible power supply operating range of 1.8 V to 3.3 V and

low power dissipation of the AD9102 make it well suited for

portable and low power applications.

PRODUCT HIGHLIGHTS

1. High Integration.

On-chip DDS and 4096 × 14 pattern memory.

2. Low Power.

Power-down mode provides for low power idle periods.

FUNCTIONAL BLOCK DIAGRAM

DAC

10kΩ

REF

100µA

1.8V

LDOs

AD9102

IOUTP

IOUTN

AVDD1

AGND

AVDD2

DVDD

DGND

DLDO1

SDIO

SCLK

RESET

REFIO

CAL_SENSE

FSADJ

CLKVDD

CLKGND

CLKN

CLDO

CLKP

1.8V

LDO

SRAM

ADDRESS

GAIN OFFSET

DAC

TIMERS + STATE MACHINE

START ADDR

START DELAY

STOP ADDR

DAC CLOCK

TRIGGER

SDO/SDI2/DOUT

DLDO2

DDS

TUNING WORD

PHASE

DAC CLOCK

DDS

SAWTOOTH

CONSTANT

DDS

RANDOM

SPI

INTERFACE

BAND

GAP

SET1

16kΩ

CLOCK

DIST

11220-001

Figure 1.

Summary of content (36 pages)

PAGE 1
Low Power, 14-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator AD9102 Data Sheet FEATURES The DDS is a 14-bit output, up to 180 MSPS master clock sine wave generator with a 24-bit tuning word, allowing 10.8 Hz/LSB frequency resolution. On-chip 4096 × 14-bit pattern memory On-chip DDS Power dissipation @ 3.3 V, 4 mA output 96.54 mW @ 180 MSPS Sleep mode: <5 mW @ 3.3 V Supply voltage: 1.8 V to 3.
PAGE 2
AD9102 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Current Outputs ........................................................... 19 Applications ....................................................................................... 1 Setting IOUTFS, DAC Gain ........................................................... 19 General Description ...................................................................
PAGE 3
Data Sheet AD9102 SPECIFICATIONS DC SPECIFICATIONS (3.3 V) TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1 and DLDO2; IOUTFS = 8 mA; maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY @ 3.3 V Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DAC OUTPUT Offset Error Gain Error Internal Reference—No Automatic IOUTFS Calibration Full-Scale Output Current 3.
PAGE 4
AD9102 Data Sheet DC SPECIFICATIONS (1.8 V) TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless otherwise noted. Table 2. Parameter RESOLUTION ACCURACY @ 1.8 V Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DAC OUTPUTS Offset Error Gain Error Internal Reference—No Automatic IOUTFS Calibration Full-Scale Output Current VCC = 1.
PAGE 5
Data Sheet AD9102 DIGITAL TIMING SPECIFICATIONS (1.8 V) TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless otherwise noted. Table 4.
PAGE 6
AD9102 Data Sheet AC SPECIFICATIONS (3.3 V) TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; IOUTFS = 8 mA; maximum sample rate, unless otherwise noted. Table 6.
PAGE 7
Data Sheet AD9102 POWER SUPPLY VOLTAGE INPUTS AND POWER DISSIPATION Table 8.
PAGE 8
AD9102 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 9.
PAGE 9
Data Sheet AD9102 32 31 30 29 28 27 26 25 TRIGGER NC NC AVDD1 IOUTN IOUTP AGND FSADJ PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9102 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 CAL_SENSE CLKVDD CLDO CLKP CLKN CLKGND REFIO NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER GROUND PLANE FOR ENHANCED ELECTRICAL AND THERMAL PERFORMANCE.
PAGE 10
AD9102 Pin No. 29 30 31 32 Mnemonic AVDD1 NC NC TRIGGER EPAD Data Sheet Description 1.8 V to 3.3 V Power Supply Input for DAC. Not Connected. Do not connect to this pin. Not Connected. Do not connect to this pin. Pattern Trigger Input. Exposed Pad. It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced electrical and thermal performance. Rev.
PAGE 11
Data Sheet AD9102 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2. –50 –50 –55 –55 SFDR SECOND HARMONIC THIRD HARMONIC –60 –65 –80 –70 –75 –80 –85 –85 –90 –90 –95 –95 –100 –100 0 10 20 30 40 50 60 70 fOUT (MHz) 0 30 40 50 60 70 60 70 70 Figure 6. SFDR at Three IOUTFS Values vs.
PAGE 12
AD9102 Data Sheet REF –5dBm MKR3 41.73MHz –90.031dBm ATTEN 18dB –130 –135 1 NSD (dBm/Hz) –140 2mA 4mA 8mA –145 –150 –155 –160 2 –165 3 10 20 30 40 50 60 70 80 90 11220-012 0 80 90 11220-013 –170 fOUT (MHz) MARKER 1 2 3 VBW 5.6kHz TRACE (1) (1) (1) TYPE FREQ FREQ FREQ X-AXIS 13.87MHz 27.87MHz 41.73MHz STOP 80MHz SWEEP 3.076s (601pts) AMPLITUDE –11.13dBm –88.70dBm –90.03dBm 11220-009 START 0Hz Figure 9. Output Spectrum, fOUT = 13.87 MHz Figure 12. NSD vs.
PAGE 13
Data Sheet AD9102 1.5 80 90 1.0 fS = 160MHz, 10MHz fS = 160MHz, 12MHz 100 PHASE NOISE (dBc/Hz) 0.5 –0.5 –1.0 2mA 4mA 8mA –1.5 110 120 130 140 150 160 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE Figure 15. INL, Three IOUTFS Values 180 100 1k 10k 100k OFFSET (Hz) Figure 16. Phase Noise vs. Offset Rev. 0 | Page 13 of 36 1M 10M 11220-016 170 –2.
PAGE 14
AD9102 Data Sheet AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V –50 –50 –55 –55 SFDR SECOND HARMONIC THIRD HARMONIC –60 –65 –75 –80 –70 –75 –80 –85 –85 –90 –90 –95 –100 0 10 20 30 40 50 60 70 fOUT (MHz) 11220-017 –95 –100 50 40 30 60 70 70 fOUT (MHz) Figure 17. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. fOUT Figure 20. SFDR at Three Temperatures vs.
PAGE 15
Data Sheet AD9102 –130 –60 –135 50MHz 100MHz 180MHz –85 –150 –155 –90 –160 –95 –165 10 40 30 20 50 60 70 80 fOUT (MHz) –170 11220-023 0 0 10 20 30 40 50 60 80 90 4000 4500 11220-027 –80 –145 4000 4500 11220-028 IMD (dBc) –75 –100 +85°C +25°C –40°C –140 NSD (dBm/Hz) –70 70 fOUT (MHz) Figure 23. IMD vs. fOUT, Three fOUT Values 11220-026 –65 Figure 26. NSD vs. fOUT at Three Temperatures 2.0 –60 2mA 4mA 4mA 2mA –65 1.5 –70 1.
PAGE 16
AD9102 Data Sheet TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.
PAGE 17
Data Sheet AD9102 FSADJ REFIO RESET CAL_SENSE AGND BAND GAP RSET1 16kΩ IREF 100µA DDS RANDOM CONSTANT DAC TIMERS + STATE MACHINE SAWTOOTH START DELAY 10kΩ SPI INTERFACE STOP ADDR START ADDR DAC CLOCK SCLK 1V AD9102 TRIGGER SDO/SDI2/DOUT CS SDIO THEORY OF OPERATION IOUTP DAC IOUTN GAIN ADDRESS OFFSET AVDD1 AVDD2 SRAM PHASE TUNING WORD DDS DAC CLOCK DDS 1.8V LDO CLOCK DIST 11220-029 CLKN CLKP CLKGND CLDO CLKVDD DGND DLDO2 DLDO1 DVDD 1.8V LDOs Figure 29.
PAGE 18
AD9102 Data Sheet SPI PORT Writing to On-Chip SRAM The AD9102 provides a flexible, synchronous serial communications (SPI) port that allows easy interfacing to ASICs, FPGAs, and industry-standard microcontrollers. The interface allows read/write access to all registers that configure the AD9102 and to the on-chip SRAM. Its data rate can be up to the SCLK clock speed listed in Table 3 and Table 4. The AD9102 includes an internal 4096 × 12 SRAM.
PAGE 19
Data Sheet AD9102 DAC TRANSFER FUNCTION Table 13 summarizes reference connections and programming. The AD9102 DAC provides a differential current output, IOUTP/IOUTN. Table 13. Reference Operation Reference Mode Internal The DAC output current equations are as follows: IOUTP = IOUTFS × DAC INPUT CODE/214 (1) REFIO Pin Connect 0.1F capacitor Connect off-chip reference External IOUTN = IOUTFS × ((214 − 1) − DAC INPUT CODE)/214 (2) where DAC INPUT CODE = 0 to 214 − 1.
PAGE 20
AD9102 Data Sheet When using automatic calibration, the following board level connections are required: CLOCK INPUT Install a resistor between the CAL_SENSE pin and AGND. To calculate the value of this resistor, use the following equation: RCAL_SENSE = 32 × VREFIO/IOUTFS where IOUTFS is the target full-scale current. Automatic calibration uses an internal clock. This calibration clock is equal to the DAC clock divided by the division factor chosen by the CAL_CLK_DIV bits of Register 0x0D.
PAGE 21
Data Sheet AD9102  Mini-Circuits® ADT1-1WT, 1:1Z 0.1µF 0.1µF XFMR CLK+ Periodic pulse trains that repeat a finite number of times are the same as those that repeat indefinitely, except that the waveforms are output during a finite number of consecutive pattern periods. CLKP 50Ω AD9102 0.1µF TRIGGER 11220-039 CLKN SCHOTTKY DIODES: HSM2812 PATTERN EXECUTED PATTERN EXECUTED PATTERN EXECUTED Figure 39.
PAGE 22
AD9102 Data Sheet tSU Pattern Period Repeat Controller The PATTERN_RPT bit in the PAT_TYPE register (Register 0x1F[0]) controls whether the pattern output auto repeats (periodic pulse train repeats indefinitely) or repeats a number of consecutive times defined by the DAC_REPEAT_CYCLE bits in Register 0x2B. The latter are periodic pulse trains that repeat a finite number of times.
PAGE 23
Data Sheet AD9102 DOUT DELAY = DOUT_START[15:0] CLKP/CLKN CYCLES The AD9102 allows SPI read/write access to the SRAM while the SRAM is actively engaged in pattern generation (RUN = 1) with some restrictions. tSU The SPI port address space for SRAM is Location 0x6000 through Location 0x6FFF. TRIGGER SRAM can be accessed using any of the SPI operating modes shown in Figure 30 through Figure 32.
PAGE 24
AD9102 Data Sheet PSEUDORANDOM SIGNAL GENERATOR • The pseudorandom noise generator generates a noise signal on each DAC output when a pseudorandom sequence is selected in the PRESTORE_SEL fields in the WAV_CONFIG register. Pseudorandom noise signals are generated as continuous waveforms only. When DVDD is 2.5 V or higher, the 1.8 V on-chip DLDO1 and DLDO2 regulators may be used. If DVVD is 1.
PAGE 25
Data Sheet AD9102 APPLICATIONS PATTERN_PERIOD SIGNAL GENERATION EXAMPLES START_DLY DAC DATA @ STOP_ADDR DATA @ START_ADDR 11220-050 Figure 47 shows a waveform stored in the 4k × 14 SRAM in an address segment defined by the START_ADDR and STOP_ADDR being output by the DAC. The waveform is repeated once during each pattern period. In each pattern period, a start delay is executed, then the pattern is read from SRAM. TRIGGER Figure 50.
PAGE 26
AD9102 Data Sheet REGISTER MAP Table 14.
PAGE 27
Data Sheet 0x3F DDS_TW1 0x43 DDS_PW 0x44 TRIG_TW_SEL 0x45 0x47 0x5C 0x5D 0x5E 0x5F 0x60 DDS_CONFIG AD9102 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] DDSTW_LSB RESERVED DDS_PHASE[15:8] DDS_PHASE[7:0] RESERVED[15:8] RESERVED[7:2] [15:8] [7:0] RESERVED [15:8] RESERVED [7:0] START_DELAY [15:8] [7:0] START_ADDR [15:8] [7:0] STOP_ADDR [15:8] [7:0] DDS_CYC [15:8] [7:0] CFG_ERROR [15:8] [7:0] RESERVED TW_RAM_ CONFIG 0x6000 SRAM_DATA to 0x6FFF [15:8] [7:0] 0x0000 RW 0x0000 RW 0x0000 RW TRIG_DELAY_ E
PAGE 28
AD9102 Data Sheet REGISTER DESCRIPTIONS SPI Control Register (SPICONFIG, Address 0x00) Table 15. Bit Descriptions for SPICONFIG Bits 15 Bit Name LSBFIRST Settings 0 1 14 SPI3WIRE 0 1 13 RESET 0 1 12 DOUBLESPI 0 1 11 SPI_DRV 0 1 10 DOUT_EN 0 1 [9:6] 5 4 2 RESERVED DOUT_ENM1 SPI_DRVM1 DOUBLESPIM1 RESETM1 1 0 SPI3WIREM1 LSBFIRSTM1 1 Description LSB first selection. MSB first per SPI standard (default). LSB first per SPI standard. Selects if SPI is using 3-wire or 4-wire interface.
PAGE 29
Data Sheet AD9102 Clock Control Register (CLOCKCONFIG, Address 0x02) Table 17. Bit Descriptions for CLOCKCONFIG Bits [15:12] 11 10 9 8 7 6 5 Bit Name RESERVED DIS_CLK RESERVED RESERVED RESERVED DIS_DCLK CLK_SLEEP CLK_PDN 4 EPS 3 DAC_INV_CLK [2:0] RESERVED Settings Description Disable the analog clock to the DAC output of the clock distribution block. Disable the analog clock to the DAC3 output of the clock distribution block.
PAGE 30
AD9102 Data Sheet FSADJ Register (DACRSET, Address 0x0C) Table 21. Bit Descriptions for DACRSET Bits 15 Bit Name DAC_RSET_EN [14:13] [12:8] RESERVED DAC_RSET_CAL [7:5] [4:0] RESERVED DAC_RSET Settings Description To write, enable the internal RSET resistor for the DAC. To read, enable RSET for DAC 1 during calibration mode.
PAGE 31
Data Sheet AD9102 Command/Status Register (PAT_STATUS, Address 0x1E) Table 25. Bit Descriptions for PAT_STATUS Bits [15:3] 3 2 1 0 Bit Name RESERVED BUF_READ MEM_ACCESS PATTERN RUN Settings Description Read back from updated buffer. Memory SPI access enable. Status of pattern being played, read only. Allows the pattern generation, and stop pattern after trigger.
PAGE 32
AD9102 Data Sheet DAC Time Control Register (PAT_TIMEBASE, Address 0x28) Table 30. Bit Descriptions for PAT_TIMEBASE Bits [15:12] [11:8] Bit Name RESERVED HOLD [7:4] PAT_PERIOD_BASE [3:0] START_DELAY_BASE Settings Description The number of times the DAC value holds the sample (0 = DAC holds for 1 sample). The number of DAC clock periods per PATTERN_PERIOD LSB (0 = PATTERN_PERIOD LSB = 1 DAC clock period).
PAGE 33
Data Sheet AD9102 DAC Digital Gain Register (DAC_DGAIN, Address 0x35) Table 36. Bit Descriptions for DAC_DGAIN Bits [15:4] [3:0] Bit Name DAC_DIG_GAIN RESERVED Settings Description DAC digital gain. Range +2 to −2. Reset 0x000 0x0 Access RW RW Reset 0x01 0x01 0x0 Access RW RW RW Reset 0x0000 Access RW Reset 0x00 0x00 Access RW RW Reset 0x0000 Access RW Reset 0x0000 0x0 Access RW RW 0x0 RW DAC Sawtooth Config Register (SAW_CONFIG, Address 0x37) Table 37.
PAGE 34
AD9102 Data Sheet Pattern Control 2 Register (DDS_CONFIG, Address 0x45) Table 42. Bit Descriptions for DDS_CONFIG Bits [15:4] 3 2 Bit Name RESERVED DDS_COS_EN DDS_MSB_EN Settings 1 PHASE_MEM_EN 0 TW_MEM_EN 0x1 0x0 0x1 0x0 Description Enables DDS cosine output of DDS instead of sine wave. Selects the SRAM address counter clock as CLKP/CLKN when set to 0x0, DDS MSB when set to 0x1. Selects the SRAM as source of DDS phase offset input. Selects the DDS_PW as the source of DDS offset.
PAGE 35
Data Sheet AD9102 Stop Address Register (STOP_ADDR, Address 0x5E) Table 46. Bit Descriptions for STOP_ADDR Bits [15:4] [3:0] Bit Name STOP_ADDR RESERVED Settings Description RAM address where DAC stops to read waveform. Reset 0x000 0x0 Access RW RW Reset 0x0001 Access RW Reset 0x0 0x000 0x0 Access R R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R DDS Cycles Register (DDS_ CYC, Address 0x5F) Table 47.
PAGE 36
AD9102 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 EXPOSED PAD 3.60 SQ 3.55 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.