Datasheet
Data Sheet AD9102
Rev. 0 | Page 17 of 36
THEORY OF OPERATION
DAC
10kΩ
I
REF
100µA
1.8V
LDOs
1V
AD9102
IOUTP
IOUTN
AVDD1
AGND
AVDD2
DVDD
DGND
DLDO1
SDIO
SCLK
RESET
REFIO
FSADJ
CLKVDD
CLKGND
CLKN
CS
CLDO
CLKP
1.8V
LDO
SRAM
ADDRESS
GAIN OFFSET
DAC
TIMERS + STATE MACHINE
START ADDR
START DELAY
STOP ADDR
DAC CLOCK
TRIGGER
SDO/SDI2/DOUT
DLDO2
DDS
TUNING WORD
PHASE
DAC CLOCK
DDS
SAWTOOTH
CONSTANT
DDS
RANDOM
SPI
INTERFACE
BAND
GAP
R
SET1
16kΩ
CLOCK
DIST
11220-029
CAL_SENSE
Figure 29. AD9102 Block Diagram
Figure 29 is a block diagram of the AD9102. The AD9102 has a
single 14-bit current output DAC.
An on-chip band gap reference is included. Optionally, an off-
chip voltage reference may be used. The full-scale DAC output
current, also known as gain, is governed by the current, I
REF
. I
REF
is the current that flows through the I
REF
resistor. The I
REF
set
resistor can be on or off chip at the user’s discretion. When the
on-chip R
SET
resistor is in use, DAC gain accuracy can be
improved by employing the built in automatic gain calibration
capability. Automatic calibration can be used with the on-chip
reference or an external REFIO voltage. A procedure for
automatic gain calibration follows.
The power supply rails for the AD9102 are AVDD for analog
circuits, CLKVDD/CLKLDO for clock input receivers, and
DVDD/DLDO1/DLDO2 for digital I/O and for the on-chip
digital datapath. AVDD, DVDD, and CLKVDD can range from
1.8 V to 3.3 V nominal. DLDO1, DLDO2, and CLDO run at
1.8 V. If DVDD = 1.8 V, connect DLDO1 and DLDO2 to
DVDD, with the on-chip LDOs disabled. All three supplies are
provided externally in this case. If CLKVDD = 1.8 V, connect
CLKVDD to CLDO with the on-chip LDOs enabled.
Digital signals input to the 14-bit DAC are generated by on-chip
digital waveform generation resources. The 14-bit samples are
input to the DAC at the CLKP/CLKN sample rate from the
digital datapath. The datapath includes gain and offset
corrections and a digital waveform source selection multiplexer.
Waveform sources are SRAM, direct digital synthesizer (DDS),
DDS output amplitude modulated by SRAM data, sawtooth
generator, dc constant, and pseudorandom sequence generator.
The waveforms output by the source selection multiplexer have
programmable pattern characteristics. The waveforms can be
set up to be continuous, continuous pulsed (fixed pattern
period and start delay within each pattern period), or finite
pulsed (a set number of pattern periods are output, then the
pattern stops).
Pulsed waveforms (finite or continuous) have a programmed
pattern period and start delay. The waveform is present in each
pulse period following the programmed pattern period start
and the start delay.
A SPI port enables loading of data into SRAM and
programming of all the control registers inside the device.