Datasheet
AD9102 Data Sheet
Rev. 0 | Page 18 of 36
SPI PORT
The AD9102 provides a flexible, synchronous serial communica-
tions (SPI) port that allows easy interfacing to ASICs, FPGAs, and
industry-standard microcontrollers. The interface allows read/write
access to all registers that configure the AD9102 and to the on-chip
SRAM. Its data rate can be up to the SCLK clock speed listed in
Table 3 and Table 4.
The SPI interface operates as a standard synchronous serial
communication port.
CS
is a low true chip select. When
CS
goes true, SPI address and data transfer begin. The first bit
coming from the SPI master on SDIO is a read write indicator
(high for read, low for write). The next 15 bits are the initial
register address. The SPI port automatically increments the
register address if
CS
stays low beyond the first data-word
allowing writes to or reads from a set of contiguous addresses.
Table 12. Command Word
MSB LSB
DB15 DB14 DB13 DB12 … DB2 DB1 DB0
R/W
A14 A13 A12 … A2 A1 A0
When the first bit of this command byte is a logic low (R/
W
bit
= 0), the SPI command is a write operation. In this case, SDIO
remains an input; see Figure 30.
COMMAND CYCLE DATA TRANSFER CYCLE
CS
SCLK
SDIO
A14
A13
A2
A1
A0
D15
N
D14
N
D13
N
D3
0
D2
0
D1
0
D0
0
R/W
11220-030
Figure 30. Serial Register Interface Timing, MSB First Write, 3-Wire SPI
When the first bit of this command byte is a logic high (R/
W
bit
= 1), the SPI command is a read operation. In this case, data is
driven out of the SPI port as shown in Figure 31 and Figure 33.
The SPI communication finishes after the
CS
pin goes high.
CS
SCLK
SDIO
A14
A13
A2
A1
A0
D15
N
D14
N
D13
N
D3
0
D2
0
D1
0
D0
0
R/W
COMMAND CYCLE DATA TRANSFER CYCLE
11220-031
Figure 31. Serial Register Interface Timing, MSB First Read, 3-Wire SPI
Writing to On-Chip SRAM
The AD9102 includes an internal 4096 × 12 SRAM. The SRAM
address space is 0x6000 to 0x6FFF of the AD9102 SPI address map.
Double SPI for Write for SRAM
The time to write data to the entire SRAM can be halved using
the SPI access mode shown in Figure 32. The SDO/SDI2/
DOUT line becomes a second serial data input line, doubling
the achievable update rate of the on-chip SRAM. SDO/SDI2/
DOUT is write only in this mode. The entire SRAM can be
written in (2 + 2 × 4096) × 8/(2 × f
SLCK
)
seconds.
CS
SCLK
SDIO
SDO/
SDI2/
DOUT
SET WAVEFORM ADDRESS
TO BE READ/WRITTEN
WAVEFORM PATTERN
ADDRESS1 = N
WAVEFORM
PATTERN DATA
WAVEFORM DATA TO BE WRITTEN
WAVEFORM PATTERN
ADDRESS2 = M
WAVEFORM
PATTERN DATA
R/W
A14
A13
A2
A1
A0
D15
N
D0
N
D15
N – 1
D0
N – 1
D15
N – 2
D1
0
D0
0
R/W = 0
ALWAYS
A14
A13
A2
A1
A0
D15
M
D0
M
D15
M – 1
D0
M – 1
D15
M – 2
D1
N + 1
D0
N + 1
11220-033
Figure 32. Double SPI Write of SRAM Data
Configuration Register Update Procedure
Most SPI accessible registers are double buffered. An active
register set controls operation of the AD9102 during pattern
generation. A set of shadow registers stores updated register
values. Register updates can be written at any time. When
configuration update is complete, the user writes a 1 to the
UPDATE bit in the RAMUPDATE register. The UPDATE bit
arms the register set for transfer from shadow registers to active
registers. The AD9102 performs this transfer automatically the
next time the pattern generator is off. This procedure does not
apply to the 4k × 14 SRAM. For the SRAM update procedure,
see the SRAM section.
Figure 33. Serial Register Interface Timing, MSB First Read, 4-Wire SPI
11220-032
CS
SCLK
SDIO
SDO/
SDI2/
DOUT
READ
R/W
A14
A13
A2
A1
A0
D
15
D
1
D
0
R/W
A14
A13
D15
N
D0
N
D1
0
D0
0
D15
N – 1
D0
N – 1
D15
N – 2
A2
A1
A0
WRITE