Datasheet

Data Sheet AD9102
Rev. 0 | Page 19 of 36
DAC TRANSFER FUNCTION
The AD9102 DAC provides a differential current output,
IOUTP/IOUTN.
The DAC output current equations are as follows:
IOUTP = I
OUTFS
× DAC INPUT CODE/2
14
(1)
IOUTN = I
OUTFS
× ((2
14
− 1) − DAC INPUT CODE)/2
14
(2)
where DAC INPUT CODE = 0 to 2
14
− 1. Full-scale current or
DAC Gain I
OUTFS
is 32 times I
REF
.
I
OUTFS
= 32 × I
REF
(3)
where I
REF
= V
REFIO
/R
SET
.
I
REF
is the current that flows through the I
REF
resistor. The I
REF
resistor may be on or off chip at the users’ discretion. When an
on-chip R
SET
resistor is in use, DAC gain accuracy can be improved
by employing the built-in automatic gain calibration capability.
ANALOG CURRENT OUTPUTS
Optimum linearity and noise performance of DAC outputs can
be achieved when they are connected differentially to an amplifier
or a transformer. In these configurations, common-mode signals
at the DAC outputs are rejected.
The output compliance voltage specifications listed in Table 1 and
Table 2 must be adhered to for the performance specifications
in those tables to be met.
SETTING I
OUTFS
, DAC GAIN
As expressed in Equation 3, DAC gain (I
OUTFS
) is a function of
the reference voltage at the REFIO terminal and R
SET
.
Voltage Reference
The AD9102 contains an internal 1.0 V nominal band gap
reference. The internal reference can be used, or replaced by a
more accurate off-chip reference. An external reference can
provide tighter reference voltage tolerances and/or lower
temperature drift than the on-chip band gap.
By default, the on-chip reference is powered up and ready to be
used. When using the on-chip reference, the REFIO terminal
needs to be decoupled to AGND using a 0.1 μF capacitor as
shown in Figure 34.
CURRENT
SCALING
x32
AD9102
DAC
I
OUTFS
R
SET
0.1µF
REFIO
I
REF
AVSS
FSADJ
V
BG
1.0V
–
+
11220-034
Figure 34. On-Chip Reference with External R
SET
Resistor
Table 13 summarizes reference connections and programming.
Table 13. Reference Operation
Reference Mode REFIO Pin
Internal
Connect 0.1F
capacitor
External Connect off-chip reference
When using an external reference, it is recommended to apply
the external reference to the REFIO pin.
Programming Internal V
REFIO
The internal REFIO voltage level is programmable.
When the internal voltage reference is in use, the BGDR field in
the lower six bits in Register 0x03 adjusts the V
REFIO
level. This
adds or subtracts up to 20% from the nominal band gap voltage
on REFIO. The voltage across the FSADJ resistor tracks this
change. As a result, I
REF
varies by the same amount. Figure 35
shows V
REFIO
vs. BGDR code for an on-chip reference with a
default voltage (BGDR = 0x00) of 1.04 V.
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0 8 16 24 32 40 48 56
CODE
V
REF
(V)
11220-035
Figure 35. Typical V
REFIO
Voltage vs. BGDR
R
SET
Resistors
R
SET
in the where statement for Equation 3 can be an internal
resistor or a board level resistor of the user’s choosing
connected to the FSADJ terminal.
To make use of the on-chip R
SET
resistor, set Bit 15 of the FSADJ
register to Logic 1. Bits[4:0] of the FSADJ register are used to
program values for the on-chip R
SET
manually.
AUTOMATIC I
OUTFS
CALIBRATION
Many applications require tight DAC gain control. The AD9102
provides an automatic I
OUTFS
calibration procedure used with an
on-chip R
SET
resistor only. The voltage reference, V
REFIO
, can be
the on-chip reference or an off-chip reference. The automatic
calibration procedure does a fine adjustment of the internal R
SET
value and the current, I
REF
.