Datasheet

Data Sheet AD9102
Rev. 0 | Page 23 of 36
TRIGGER
CLKP/
CLKN
DOUT DELAY =
DOUT_START[15:0] CLKP/CLKN CYCLES
DOUT
t
SU
11220-044
Figure 44. DOUT Start Sequence
CLKP/CLKN
PATTERN
G
ENERATOR
STATE
DOUT
PATTERN ON PATTERN OFF
PATTERN
STOPS
DOUT DELAY = DOUT_STOP[3:0]
CLKP/CLKN CYCLES
11220-045
Figure 45. DOUT Stop Sequence
DIRECT DIGITAL SYNTHESIZER (DDS)
The DDS generates sinusoid at a frequency determined by its
tuning word input. The tuning word is 24 bits wide. The
resolution of DDS tuning is f
CLKP/N
/2
24
. The DDS output
frequency is DDS_TW × f
CLKP/N
/2
24
.
The DDS tuning word is programmed using one of two methods.
For a fixed frequency, the DDSTW_MSB and DDSTW_LSB bit
fields are programmed with a constant. When the frequency
of the DDS needs to change within each pattern period, a sequence
of values stored in SRAM is combined with a selection of
DDSTW_MSB bits to form the tuning word.
SRAM
The AD9102 4k × 14 SRAM can contain signal samples,
amplitude modulation patterns, lists of DDS tuning words, or
lists of DDS output phase offset words. Any SRAM data address
can be written to and read from the SPI port as long as the
SRAM is not actively engaged in pattern generation (RUN bit =
0). To write to any SRAM address, set up the PAT_STATUS
register (Register 0x1E) as follows:
 BUF_READ = 0
 MEM_ACCESS = 1
 RUN = 0
To read data from any SRAM address, set up the PAT_STATUS
as follows:
 BUF_READ = 1
 MEM_ACCESS = 1
 RUN = 0
The AD9102 allows SPI read/write access to the SRAM while
the SRAM is actively engaged in pattern generation (RUN = 1)
with some restrictions.
The SPI port address space for SRAM is Location 0x6000
through Location 0x6FFF.
SRAM can be accessed using any of the SPI operating modes
shown in Figure 30 through Figure 32. Using the SPI modes of
operation shown in Figure 31 and Figure 33, the entire SRAM
can be written in (2 + 2 × 4096) ×8/f
SLCK
seconds.
When the PAT_STATUS register RUN bit =1 (pattern generation
enabled) data is read using the SRAM address counter. The
address counter has a START_ADDR (start address) and
STOP_ADDR (stop address). During each pattern period, data
is read from SRAM after the START_DELAY period and while
each address counter is incrementing.
While the PAT_STATUS register RUN bit = 1 (pattern generation
enabled), data can be written to or read from SRAM via the SPI
port outside the address range defined by START_ADDR and
STOP_ADDR.
Incrementing Pattern Generation Mode SRAM Address
Counters
The SRAM address counter can be programmed to be incremented
by CLKP/CLKN (default) or by the rising edge of the DDS MSB.
The DDS_MSB_EN bit in the DDS_CONFIG register makes
this selection. For example, DDS MSB can be used to clock the
address counter when generating a chirp waveform from the
DDS using a list of tuning words in SRAM. Each frequency setting
dwells for one DDS output sine wave cycle.
SAWTOOTH GENERATOR
When sawtooth is selected in the PRESTORE_SEL bits in the
WAV_CONFIG register, the sawtooth generator is connected to
the DAC digital datapath.
Sawtooth types, shown in Figure 46, are selected using the
SAW_TYPE bits in the SAW_CONFIG register. The number of
samples per sawtooth waveform step is programmed in the
SAW_STEP bits.
POSITIVE
SAWTOOTH
NEGATIVE
SAWTOOTH
TRIANGLE
WAVE
11220-046
Figure 46. Sawtooth Patterns