Datasheet

Data Sheet AD9102
Rev. 0 | Page 25 of 36
APPLICATIONS
SIGNAL GENERATION EXAMPLES
Figure 47 shows a waveform stored in the 4k × 14 SRAM in an
address segment defined by the START_ADDR and STOP_ADDR
being output by the DAC. The waveform is repeated once
during each pattern period. In each pattern period, a start delay
is executed, then the pattern is read from SRAM.
PATTERN
EXECUTED
PATTERN
EXECUTED
PATTERN
EXECUTED
TRIGGER
DAC
PATTERN_PERIOD
START_DLY
DATA @
START_ADDR
DATA @
STOP_ADDR
11220-047
Figure 47. Pattern in SRAM
Figure 48 shows a pulsed sine wave generated by the DAC. The
DDS generates a sine wave at a programmed frequency. The
DAC input datapath is programmed with a start delay and a
number of sine wave cycles to output.
11220-048
DAC
START_DLY #CYCLES
PATTERN_PERIOD
Figure 48. Pulsed Sine Wave in Pattern Periods
Figure 49 shows a sawtooth wave shape generated by the DAC
in successive pattern periods with a start delay.
11220-049
DAC
START_DLY
PATTERN_PERIOD
Figure 49. Pulsed Sawtooth Waveform in Pattern Periods
Figure 50 shows the DAC outputting a sine wave modulated by
an amplitude envelope. The sine wave is generated by the DDS,
and the amplitude envelope is stored in SRAM. A start delay
and a digital gain factor are applied in the DAC input datapath.
11220-050
DAC
START_DLY
PATTERN_PERIOD
DATA @
START_ADDR
DATA @
STOP_ADDR
Figure 50. DDS Output Amplitude Modulated by SRAM Envelope
Figure 51 and Figure 52 show the DAC generating continuous
waveforms, one with start delays, one without.
DAC
START_DLY
11220-051
Figure 51. Waveform with Start Delays
DAC
11220-052
Figure 52. Waveform Without Start Delays
Figure 53 shows an FSK modulated signal generated using a list
of DDS tuning word bit fields stored in SRAM. The SRAM
address counter is incremented by the rising edge of the DDS
output MSB.
SYMBOL0
DAC
SYMBOL1 SYMBOL2 SYMBOL3 SYMBOL4 SYMBOL5
RAM WORD
01 23 45 67 89 1011
RAM WORD RAM WORD RAM WORD RAM WORD RAM WORD
11220-053
Figure 53. FSK Modulated Signal