Datasheet

Data Sheet AD9102

Rev. 0 | Page 27 of 36

0x3F DDS_TW1 [15:8] DDSTW_LSB 0x0000 RW

[7:0] RESERVED

0x43 DDS_PW [15:8] DDS_PHASE[15:8] 0x0000 RW

[7:0] DDS_PHASE[7:0]

0x44 TRIG_TW_SEL [15:8] RESERVED[15:8] 0x0000 RW

[7:0] RESERVED[7:2]

TRIG_DELAY_

RESERVED

0x45 DDS_CONFIG [15:8] RESERVED 0x0000 RW

[7:0] RESERVED DDS_COS_EN

DDS_MSB_

PHASE_MEM_

TW_MEM_EN

0x47

TW_RAM_

CONFIG

[15:8] RESERVED RESERVED 0x0000 RW

[7:0] RESERVED TW_MEM_SHIFT

0x5C START_DELAY [15:8] START_DELAY[15:8] 0x0000 RW

[7:0] START_DELAY[7:0]

0x5D START_ADDR [15:8] START_ADDR[15:8] 0x0000 RW

[7:0] START_ADDR[7:5] RESERVED

0x5E STOP_ADDR [15:8] STOP_ADDR[15:8] 0x0000 RW

[7:0] STOP_ADDR[7:5] RESERVED

0x5F DDS_CYC [15:8] DDS_CYC[15:8] 0x0001 RW

[7:0] DDS_CYC[7:0]

0x60 CFG_ERROR [15:8] ERROR_CLEAR RESERVED 0x0000 R

[7:0] RESERVED

DOUT_START_

LG_ERR

PAT_DLY_

SHORT_ERR

DOUT_START_

SHORT_ERR

PERIOD_

SHORT_ERR

ODD_ADDR_

ERR

MEM_READ_

ERR

0x6000

0x6FFF

SRAM_DATA [15:8] RESERVED SRAM_DATA[11:8] N/A RW

[7:0] SRAM_DATA[7:0]