Datasheet
AD9102 Data Sheet
Rev. 0 | Page 28 of 36
REGISTER DESCRIPTIONS
SPI Control Register (SPICONFIG, Address 0x00)
Table 15. Bit Descriptions for SPICONFIG
Bits Bit Name Settings Description Reset Access
15 LSBFIRST LSB first selection. 0x0 RW
0 MSB first per SPI standard (default).
1 LSB first per SPI standard.
14 SPI3WIRE Selects if SPI is using 3-wire or 4-wire interface. 0x0 RW
0 4-wire SPI.
1 3-wire SPI.
13 RESET
Executes software reset of SPI and controllers, reloads default register values,
except Register 0x00.
0x0 RW
0 Normal status.
1 Reset whole register map, except 0x0000.
12 DOUBLESPI Double SPI data line. 0x0 RW
0 The SPI port has only 1 data line and can be used as a 3-wire or 4-wire interface.
1
The SPI port has two data lines both bi-directional defining a pseudo dual 3-
wire interface where
CS
and SCLK are shared between the two ports. This mode
is available only for RAM data read or write.
11 SPI_DRV Double drive ability for SPI output. 0x0 RW
0 Single SPI output drive ability.
1 Two time drive ability on SPI output.
10 DOUT_EN Enable DOUT signal on SDO/SDI2/DOUT pin. 0x0 RW
0 SDO/SDI2 function input/output.
1 DOUT function output.
[9:6] RESERVED RW
5 DOUT_ENM
1
Enable DOUT signal on SDO/SDI2/DOUT pin. RW
4 SPI_DRVM
1
Double drive ability for SPI output. 0x0 RW
DOUBLESPIM
1
Doube SPI data line. 0x0 RW
2 RESETM
1
Executes software reset of SPI and controllers, reloads default register values,
except Register 0x00.
0x0 RW
1 SPI3WIREM
1
Selects whether SPI uses a 3-wire or 4-wire interface. 0x0 RW
0 LSBFIRSTM
1
LSB first selection. 0x0 RW
1
SPICONFIG[10:15] must always be set to the mirror of SPICONFIG[5:0] to allow easy recovery of the SPI operation when LSBFIRST bit is set incorrectly. (Bit 15 = Bit 0, Bit 14 = Bit 1,
Bit 13 = Bit 2, Bit 12 = Bit 3, Bit 11 = Bit 4, and Bit 10 = Bit 5.)
Power Status Register (POWERCONFIG, Address 0x01)
Table 16. Bit Descriptions for POWERCONFIG
Bits Bit Name Settings Description Reset Access
[15:12] RESERVED 0x0 RW
11 CLK_LDO_STAT Read-only flag indicating CLKVDD LDO is on. 0x0 R
10 DIG1_LDO_STAT Read-only flag indicating DVDD1 LDO is on. 0x0 R
9 DIG2_LDO_STAT Read-only flag indicating DVDD2 LDO is on. 0x0 R
8 PDN_LDO_CLK Disable the CLKVDD LDO. An external supply is required. 0x0 RW
7 PDN_LDO_DIG1 Disable the DVDD1 LDO. An external supply is required. 0x0 RW
6 PDN_LDO_DIG2 Disable the DVDD2 LDO. An external supply is required. 0x0 RW
5 REF_PDN Power down on-chip REFIO. 0x0 RW
4 REF_EXT Always set to 0. 0x0 RW
3 DAC_SLEEP Disable DAC output current. 0x0 RW
2 RESERVED Disable DAC2 output current. 0x0 RW
1 RESERVED Disable DAC3 output current. 0x0 RW
0 RESERVED Disable DAC4 output current. 0x0 RW