Datasheet
AD9102 Data Sheet
Rev. 0 | Page 30 of 36
FSADJ Register (DACRSET, Address 0x0C)
Table 21. Bit Descriptions for DACRSET
Bits Bit Name Settings Description Reset Access
15 DAC_RSET_EN
To write, enable the internal R
SET
resistor for the DAC. To read, enable R
SET
for DAC 1 during calibration mode.
0x0 RW
[14:13] RESERVED 0x0 RW
[12:8] DAC_RSET_CAL
Digital control for the value of the R
SET
resistor for the DAC after
calibration; read only.
0x00 R
[7:5] RESERVED 0x0 RW
[4:0] DAC_RSET Digital control to set the value of the R
SET
resistor in the DAC . 0x0A RW
Calibration Register (CALCONFIG, Address 0x0D)
Table 22. Bit Descriptions for CALCONFIG
Bits Bit Name Settings Description Reset Access
15 RESERVED 0x0 RW
14 COMP_OFFSET_OF Compensation offset calibration value overflow. 0x0 R
13 COMP_OFFSET_UF Compensation offset calibration value underflow. 0x0 R
12 RSET_CAL_OF R
SET
calibration value overflow. 0x0 R
11 RSET_CAL_UF R
SET
calibration value underflow. 0x0 R
10 GAIN_CAL_OF Gain calibration value overflow. 0x0 R
9 GAIN_CAL_UF Gain calibration value underflow. 0x0 R
8 CAL_RESET Pulse this bit high and low to reset the calibration results. 0x0 RW
7 CAL_MODE Read-only flag indicating calibration is being used. 0x0 R
6 CAL_MODE_EN Enables the gain calibration circuitry. 0x0 RW
[5:4] COMP_CAL_RNG Offset calibration range. 0x0 RW
3 CAL_CLK_EN Enables the calibration clock to the calibration circuitry. 0x0 RW
[2:0] CAL_CLK_DIV Sets divider from the DAC clock to the calibration clock. 0x0 RW
Comp Offset Register (COMPOFFSET, Address 0x0E)
Table 23. Bit Descriptions for COMPOFFSET
Bits Bit Name Settings Description Reset Access
15 RESERVED 0x0 RW
[14:8]
COMP_OFFSET_CA
L
The result of the offset calibration for the comparator. 0x00 R
[7:2] RESERVED 0x00 RW
1 CAL_FIN Read-only flag indicating calibration is completed. 0x0 R
0 START_CAL Start a calibration cycle. 0x0 RW
Update Pattern Register (RAMUPDATE, Address 0x1D)
Table 24. Bit Descriptions for RAMUPDATE
Bits Bit Name Settings Description Reset Access
[15:1] RESERVED 0x0000 RW
0 UPDATE Update all SPI settings with a new configuration (self-clearing). 0x0 RW