Datasheet

AD9102 Data Sheet
Rev. 0 | Page 32 of 36
DAC Time Control Register (PAT_TIMEBASE, Address 0x28)
Table 30. Bit Descriptions for PAT_TIMEBASE
Bits Bit Name Settings Description Reset Access
[15:12] RESERVED 0x0 RW
[11:8] HOLD
The number of times the DAC value holds the sample (0 = DAC holds for
1 sample).
0x1 RW
[7:4] PAT_PERIOD_BASE
The number of DAC clock periods per PATTERN_PERIOD LSB (0 =
PATTERN_PERIOD LSB = 1 DAC clock period).
0x1 RW
[3:0] START_DELAY_BASE
The number of DAC clock periods per START_DELAY × LSB (0 =
START_DELAY × LSB = 1 DAC clock period).
0x1 RW
Pattern Period Register (PAT_PERIOD, Address 0x29)
Table 31. Bit Descriptions for PAT_PERIOD
Bits Bit Name Settings Description Reset Access
[15:0] PATTERN_PERIOD Pattern period register. 0x8000 RW
DAC Pattern Repeat Cycles Register (DAC_PAT, Address 0x2B)
Table 32. Bit Descriptions for DAC_PAT
Bits Bit Name Settings Description Reset Access
[15:8] RESERVED 0x01 RW
[7:0]
DAC_REPEAT_CYCLE
The number of DAC pattern repeat cycles + 1.
0x01
RW
TRIGGER
Start to DOUT Signal Register (DOUT_START, Address 0x2C)
Table 33. Bit Descriptions for DOUT_START
Bits Bit Name Settings Description Reset Access
[15:0]
DOUT_START
Time between when the
TRIGGER
pin is low and DOUT signal is high in
the number of DAC clock cycles.
0x0003
RW
DOUT CONFIG Register (DOUT_CONFIG, Address 0x2D)
Table 34. Bit Descriptions for DOUT_CONFIG
Bits Bit Name Settings Description Reset Access
[15:6] RESERVED 0x000 RW
5 DOUT_VAL
Manually sets the DOUT signal value; it is valid only when DOUT_MODE
= 0 (manual mode).
0x0 RW
4 DOUT_MODE Set different enable signal mode. 0x0 RW
0x0
DOUT pin is output from SDO/SDI2/DOUT pin and manually controlled
by Bit 5, DOUT_EN in Register 0x00 must be set to use this feature.
0x1
DOUT pin is output from SDO/SDI2/DOUT. The pin is controlled by
DOUT_START and DOUT_STOP. DOUT_EN in Register 0x00 must be set to
use this feature.
[3:0] DOUT_STOP
Time between pattern end and DOUT signal low in number of DAC clock
cycles.
0x0 RW
DAC Constant Value Register (DAC_CST, Address 0x31)
Table 35. Bit Descriptions for DAC_CST
Bits Bit Name Settings Description Reset Access
[15:4] DAC_CONST Most significant byte of DAC constant value 0x0000 RW
[3:0] RESERVED 0x0 RW