Datasheet

Data Sheet AD9102
Rev. 0 | Page 33 of 36
DAC Digital Gain Register (DAC_DGAIN, Address 0x35)
Table 36. Bit Descriptions for DAC_DGAIN
Bits Bit Name Settings Description Reset Access
[15:4] DAC_DIG_GAIN DAC digital gain. Range +2 to −2. 0x000 RW
[3:0] RESERVED 0x0 RW
DAC Sawtooth Config Register (SAW_CONFIG, Address 0x37)
Table 37. Bit Descriptions for SAW_CONFIG
Bits Bit Name Settings Description Reset Access
[15:8] RESERVED 0x01 RW
[7:2] SAW_STEP Number of samples per step for the DAC. 0x01 RW
[1:0] SAW_TYPE The type of sawtooth (positive, negative or triangle) for DAC. 0x0 RW
0
Ramp up sawtooth wave.
1 Ramp down sawtooth wave.
2 Triangle sawtooth wave.
3 No wave, zero.
DDS Tuning Word MSB Register (DDS_TW32, Address 0x3E)
Table 38. Bit Descriptions for DDS_TW32
Bits Bit Name Settings Description Reset Access
[15:0] DDSTW_MSB DDS tuning word MSB. 0x0000 RW
DDS Tuning Word LSB Register (DDS_TW1, Address 0x3F)
Table 39. Bit Descriptions for DDS_TW1
Bits Bit Name Settings Description Reset Access
[15:8] DDSTW_LSB DDS tuning word LSB. 0x00 RW
[7:0] RESERVED 0x00 RW
DDS Phase Offset Register (DDS_PW, Address 0x43)
Table 40. Bit Descriptions for DDS1_PW
Bits Bit Name Settings Description Reset Access
[15:0] DDS_PHASE DDS phase offset. 0x0000 RW
Pattern Control 1 Register (TRIG_TW_SEL, Address 0x44)
Table 41. Bit Descriptions for TRIG_TW_SEL
Bits Bit Name Settings Description Reset Access
[15:2] RESERVED 0x0000 RW
1 TRIG_DELAY_EN Enable start delay as trigger delay for all 4 channels. 0x0 RW
0
Delay repeats for all patterns.
1 Delay is only at the start of first pattern.
0 RESERVED 0x0 RW