Datasheet

AD9102 Data Sheet
Rev. 0 | Page 34 of 36
Pattern Control 2 Register (DDS_CONFIG, Address 0x45)
Table 42. Bit Descriptions for DDS_CONFIG
Bits Bit Name Settings Description Reset Access
[15:4] RESERVED 0x0 RW
3 DDS_COS_EN Enables DDS cosine output of DDS instead of sine wave. 0x0 RW
2 DDS_MSB_EN
Selects the SRAM address counter clock as CLKP/CLKN when set to 0x0,
DDS MSB when set to 0x1.
0x0 RW
1
PHASE_MEM_EN
0x1
Selects the SRAM as source of DDS phase offset input.
0x0
RW
0x0 Selects the DDS_PW as the source of DDS offset.
0 TW_MEM_EN 0x1
Selects the SRAM and DDS_TW registers as configured in the
TW_RAM_CONFIG register as the source of DDS tuning word input.
0x0 RW
0x0 Selects the DDS_TW registers as the source for DS tuning words
TW_RAM_CONFIG Register (TW_RAM_CONFIG, Address 0x47)
Table 43. Bit Descriptions for TW_RAM_CONFIG
Bits Bit Name Settings Description Reset Access
[15:5] RESERVED 0x000 RW
[4:0] TW_MEM_SHIFT
TW_MEM_EN1 is set. This register controls the right shift bit when memory
data merge to DDS1TW.
0x00 RW
0x00 DDSTW = {RAM[13:0],10'b0}
0x01 DDSTW = {DDSTW[23],RAM[13:0],9'b0}
0x02 DDSTW = {DDSTW[23:22],RAM[13:0],8'b0}
0x03 DDSTW = {DDSTW[23:21],RAM[13:0],7'b0}
0x04
DDSTW = {DDSTW[23:20],RAM[13:0],6'b0}
0x05 DDSTW = {DDSTW[23:19],RAM[13:0],5'b0}
0x06 DDSTW = {DDSTW[23:18],RAM[13:0],4'b0}
0x07 DDSTW = {DDSTW[23:17],RAM[13:0],3'b0}
0x08 DDSTW = {DDSTW[23:16],RAM[13:0],2'b0}
0x09 DDSTW = {DDSTW[23:15],RAM[13:0],1'b0}
0x0A
DDSTW = {DDSTW[23:14],RAM[13:0]}
0x0B DDSTW = {DDSTW[23:13],RAM[13:1]}
0x0C DDSTW = {DDSTW[23:12],RAM[13:2]}
0x0D DDSTW = {DDSTW[23:11],RAM[13:3]}
0x0E DDSTW = {DDSTW[23:10],RAM[13:4]}
0x0F DDSTW = {DDSTW[23:9],RAM[13:5]}
0x10
DDSTW = {DDSTW[23:8],RAM[13:6]}
x Reserved
Start Delay Register (START_DLY, Address 0x5C)
Table 44. Bit Descriptions for START_DLY
Bits Bit Name Settings Description Reset Access
[15:0] START_DELAY Start delay of DAC. 0x0000 RW
Start Address Register (START_ADDR, Address 0x5D)
Table 45. Bit Descriptions for START_ADDR
Bits
Bit Name
Settings
Description
Reset
Access
[15:4] START_ADDR RAM address where DAC starts to read waveform. 0x000 RW
[3:0] RESERVED 0x0 RW