Datasheet

AD9102 Data Sheet
Rev. 0 | Page 4 of 36
DC SPECIFICATIONS (1.8 V)
T
MIN
to T
MAX
; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; I
OUTFS
= 4 mA; maximum sample rate, unless
otherwise noted.
Table 2.
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY @ 1.8 V
Differential Nonlinearity (DNL) ±1.5 LSB
Integral Nonlinearity (INL) ±1.4 LSB
DAC OUTPUTS
Offset Error ±0.00025 % of FSR
Gain Error Internal Reference—No Automatic I
OUTFS
Calibration −1.0 +1.0 % of FSR
Full-Scale Output Current
V
CC
= 1.8 V 2 4 4 mA
Output Resistance 200 MΩ
Output Compliance Voltage
−0.5
+1.0
V
DAC TEMPERATURE DRIFT
Gain ±228 ppm/°C
Reference Voltage
±131
ppm/°C
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 1.8 V 0.8 1.0 1.2 V
Output Resistance 10 kΩ
REFERENCE INPUT
Voltage Compliance
0.1
1.25
V
Input Resistance External Reference Mode 1 MΩ
DIGITAL TIMING SPECIFICATIONS (3.3 V)
T
MIN
to T
MAX
; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; I
OUTFS
= 8 mA; maximum sample rate,
unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate 180 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 80 MHz
Minimum Pulse Width High 6.25 ns
Minimum Pulse Width Low 6.25 ns
Setup Time SDIO to SCLK 4.0 ns
Hold Time SDIO to SCLK
5.0
ns
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO 6.2 ns
Setup Time CS to SCLK
4.0 ns