Datasheet

Data Sheet AD9102
Rev. 0 | Page 5 of 36
DIGITAL TIMING SPECIFICATIONS (1.8 V)
T
MIN
to T
MAX
; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; I
OUTFS
= 4 mA; maximum sample rate, unless
otherwise noted.
Table 4.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate 180 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 80 MHz
Minimum Pulse Width High 6.25 ns
Minimum Pulse Width Low 6.25 ns
Setup Time SDIO to SCLK 4.0 ns
Hold Time SDIO to SCLK
5.0
ns
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO 8.8 ns
Setup Time CS to SCLK
4.0 ns
INPUT/OUTPUT SIGNAL SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO,
SDO/SDI2/DOUT, RESET, TRIGGER)
Input V
IN
Logic High DVDD = 1.8 V 1.53 V
DVDD = 3.3 V 2.475 V
Input V
IN
Logic Low DVDD = 1.8 V 0.27 V
DVDD = 3.3 V 0.825 V
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)
Output V
OUT
Logic High DVDD = 1.8 V 1.79 V
DVDD = 3.3 V
3.28
V
Output V
OUT
Logic Low DVDD = 1.8 V 0.25 V
DVDD = 3.3 V 0.625 V
DAC CLOCK INPUT (CLKP, CLKN)
Minimum Peak-to-Peak Differential Input Voltage,
V
CLKP
/V
CLKN
150 mV
Maximum Voltage at V
CLKP
or V
CLKN
V
DVDD
V
Minimum Voltage at V
CLKP
or V
CLKN
V
DGND
V
Common-Mode Voltage Generated on Chip 0.9 V