Dual, 16-Bit, 1000 MSPS, TxDAC+ Digital-to-Analog Converter AD9125 FEATURES GENERAL DESCRIPTION Flexible CMOS interface allows dual-word, word, or byte load Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.
AD9125 TABLE OF CONTENTS Features .............................................................................................. 1 NCO Modulation ....................................................................... 35 Applications ....................................................................................... 1 Datapath Configuration ............................................................ 35 General Description .........................................................................
AD9125 FUNCTIONAL BLOCK DIAGRAM D[31:0] DATA RECEIVER 16 1.2G IOUT1P DAC 1 AUX 16-BIT IOUT1N 16 FIFO fDATA /2 PRE MOD NCO AND MOD HB1 HB2 10 HB3 I OFFSET Q OFFSET INV SINC DACCLK 16 DCI 16 10 1.
AD9125 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.
AD9125 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2.
AD9125 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4.
AD9125 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD33 IOVDD DVDD18, CVDD18 AVSS EPAD CVSS DVSS FSADJ, REFIO, IOUT1P/IOUT1N, IOUT2P/IOUT2N D[31:0], FRAME, DCI DACCLKP/DACCLKN, REFCLKP/REFCLKN RESET, IRQ, CS, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range The exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead LFCSP. The EPAD performs as an electrical and thermal connection to the board.
AD9125 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CVDD18 CVDD18 REFCLKP REFCLKN AVDD33 IOUT1P IOUT1N AVDD33 AVSS FSADJ REFIO AVSS AVDD33 IOUT2N IOUT2P AVDD33 AVSS NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9125 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RESET CS SCLK SDIO SDO DVDD18 D0 D1 D2 D3 DVSS DVDD18 D4 D5 D6 D7 D8 D9 NOTES 1. NC = NO CONNECT. 2.
AD9125 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic NC DVDD18 DVSS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 DVDD18 DVSS D3 D2 D1 D0 DVDD18 SDO SDIO SCLK CS RESET NC AVSS AVDD33 IOUT2P IOUT2N AVDD33 AVSS REFIO FSADJ AVSS AVDD33 IOUT1N IOUT1P AVDD33 REFCLKN REFCLKP CVDD18 CVDD18 EPAD Description No Connect. 1.8 V Digital Supply. Digital Common. Data Bit 15. Data Bit 14. Data Bit 13. Data Bit 12.
AD9125 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 0dBFS –6dBFS –12dBFS –18dBFS –55 –60 –30 HARMONICS (dBc) HARMONICS (dBc) –50 fDATA = 125MSPS, SECOND HARMONIC fDATA = 125MSPS, THIRD HARMONIC fDATA = 250MSPS, SECOND HARMONIC fDATA = 250MSPS, THIRD HARMONIC –40 –50 –60 –70 –65 –70 –75 –80 –80 –85 –90 50 100 150 200 250 300 fOUT (MHz) 09016-101 0 200 250 300 0dBFS –6dBFS –12dBFS –18dBFS –55 –60 –30 –40 –50 –60 –70 –65 –70 –75 –80 –85 –80 –90 –90 –95 100 200 300 400 500
AD9125 –50 fDATA = 125MSPS fDATA = 250MSPS HIGHEST DIGITAL SPUR (dBc) –55 2× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 250MSPS, fOUT = 101MHz –60 –65 –70 –75 –80 –85 0 50 100 150 200 250 300 fOUT (MHz) 09016-107 –95 fDATA = 125MSPS fDATA = 250MSPS HIGHEST DIGITAL SPUR (dBc) –55 VBW 10kHz STOP 500.0MHz SWEEP 6.017s (601 PTS) Figure 13. 2× Interpolation, Single-Tone Spectrum Figure 10. Highest Digital Spur vs.
AD9125 –50 –55 –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 50 100 150 200 250 300 fOUT (MHz) 0 150 200 250 300 Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 250 MSPS, fSC = 20 mA –50 fDATA = 125MSPS fDATA = 250MSPS –55 100 fOUT (MHz) Figure 16. IMD vs.
AD9125 –154 –160 –156 2×, fDATA = 250MSPS 4×, fDATA = 125MSPS 8×, fDATA = 125MSPS –161 –158 NSD (dBm/Hz) NSD (dBm/Hz) –162 –160 –162 –163 –164 –164 2×, fDATA = 250MSPS 4×, fDATA = 125MSPS 8×, fDATA = 125MSPS –166 –165 100 200 300 400 500 600 fOUT (MHz) 0 –161.5 200 250 300 350 400 450 500 0dBFS –6dBFS –12dBFS –18dBFS –162.0 –162.5 –158 –163.0 NSD (dBm/Hz) NSD (dBm/Hz) 150 Figure 25. Eight-Tone NSD vs.
AD9125 –77 –50 0dBFS –3dBFS –6dBFS –78 ACLR (dBc) –80 –81 –82 –65 –70 –75 –80 –83 –85 –84 50 100 150 200 250 fOUT (MHz) 09016-125 –90 0 Figure 28. One-Carrier W-CDMA ACLR vs. fOUT over Digital Cutback, Adjacent Channel, PLL Off 0 100 200 300 400 500 fOUT (MHz) 09016-128 ACLR (dBc) PLL OFF PLL OFF PLL ON PLL ON –60 –79 Figure 31. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation Rate, Adjacent Channel, PLL On vs.
AD9125 FREQ OFFSET 5.00MHz 10.00MHz 15.00MHz REF BW 3.840MHz 3.840MHz 2.888MHz LOWER dBc dBm –75.96 –85.96 –85.33 –95.33 –95.81 –95.81 UPPER dBc dBm –77.13 –87.13 –85.24 –95.25 –85.43 –95.43 VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) TOTAL CARRIER POWER: –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER: –16.89dBm/3.84000MHz 1 2 3 4 Figure 34. Four-Carrier W-CDMA ACLR Performance, IF ≈150 MHz –16.92dBm –16.89dBm –17.43dBm –17.64dBm OFFSET FREQ 5.000MHz 10.00MHz 15.
AD9125 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.
AD9125 THEORY OF OPERATION The AD9125 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9125 allows wider bandwidths and more carriers to be synthesized than in previously available DACs.
AD9125 SERIAL PORT OPTIONS INSTRUCTION CYCLE When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from the high address to the low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle.
AD9125 DEVICE CONFIGURATION REGISTER MAP Table 10.
AD9125 Register Name FTW 1 (LSB) Addr (Hex) 0x30 FTW 2 0x31 FTW[15:8] 0x00 FTW 3 0x32 FTW[23:16] 0x00 FTW 4 (MSB) 0x33 FTW[31:24] 0x00 NCO Phase Offset LSB NCO Phase Offset MSB NCO FTW Update 0x34 NCO phase offset[7:0] 0x00 0x35 NCO phase offset[15:8] 0x00 I Phase Adj LSB 0x38 I Phase Adj MSB 0x39 Q Phase Adj LSB 0x3A Q Phase Adj MSB 0x3B I DAC Offset LSB 0x3C I DAC offset[7:0] 0x00 I DAC Offset MSB 0x3D I DAC offset[15:8] 0x00 Q DAC Offset LSB 0x3E Q DAC offset[7:0]
AD9125 Register Name Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Die Revsion Addr (Hex) 0x6F Bit 7 Bit 6 Bit 5 0x70 0x71 0x72 0x73 0x7F Bit 4 Bit 3 Compare Value Q1[15:8] Bit 2 Bit 1 Bit 0 Default 0xAA Errors detected I_BITS[7:0] Errors detected I_BITS[15:8] Errors detected Q_BITS[7:0] Errors detected Q_BITS[15:8] Revision[3:0] 0x00 0x00 0x00 0x00 0x0C DEVICE CONFIGURATION REGISTER DESCRIPTIONS Table 11.
AD9125 Register Name Address (Hex) Interrupt Enable 2 0x05 Bits 1 0 7 6 5 4 1 0 7 Name Enable FIFO Warning 1 Enable FIFO Warning 2 Set to 0 Set to 0 Set to 0 Enable AED comparison pass Enable AED comparison fail Enable SED comparison fail Set to 0 Set to 0 PLL lock lost 6 PLL locked 5 Sync signal lost 4 Sync signal locked 3 Sync phase locked 2 Soft FIFO sync 1 FIFO Warning 1 0 FIFO Warning 2 4 AED comparison pass 3 AED comparison fail 2 SED comparison fail 7 6 5 DACCLK duty corre
AD9125 Register Name PLL Control 1 PLL Control 2 PLL Control 3 PLL Status 1 Address (Hex) 0x0A 0x0C 0x0D 0x0E Bits 7 Name PLL enable 6 PLL manual enable [5:0] [7:5] Manual VCO band PLL loop bandwidth[2:0] [4:0] PLL charge pump current[4:0] [7:6] N2[1:0] 4 [3:2] PLL cross control enable N0[1:0] [1:0] N1[1:0] 7 PLL lock [3:0] PLL Status 2 0x0F [5:0] Sync Control 1 0x10 7 6 VCO control voltage[3:0] VCO band readback[5:0] Sync enable Data/FIFO rate toggle 3 Rising edge sync [2:0
AD9125 Register Name Address (Hex) Bits Name Sync Control 2 0x11 5:0 Sync phase request[5:0] Sync Status 1 0x12 7 Sync lost Sync Status 2 0x13 6 [7:0] Sync locked Sync phase readback[7:0] FIFO Control 0x17 [2:0] FIFO phase offset[2:0] FIFO Status 1 0x18 7 6 2 1 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request 0 FIFO reset aligned [7:0] 7 6 5 3 FIFO level[7:0] Bypass premod Bypass sinc−1 Bypass NCO NCO gain 2 Bypass phase compensation and dc offse
AD9125 Register Name HB1 Control Address (Hex) 0x1C Bits 1 Name Select sideband 0 Send I data to Q data [2:1] HB1[1:0] 0 Bypass HB1 HB2 Control 0x1D [6:1] HB2[5:0] 0 Bypass HB2 HB3 Control 0x1E [6:1] HB3[5:0] Chip ID 0x1F 0 [7:0] Bypass HB3 Chip ID[7:0] Description 0 = the modulator outputs high-side image. 1 = the modulator outputs low-side image. The image is spectrally inverted compared with the input data.
AD9125 Register Name FTW 1 (LSB) Address (Hex) 0x30 Bits [7:0] Name FTW[7:0] FTW 2 FTW 3 FTW 4 (MSB) NCO Phase Offset LSB 0x31 0x32 0x33 0x34 [7:0] [7:0] [7:0] [7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO phase offset[7:0] NCO Phase Offset MSB NCO FTW Update 0x35 [7:0] NCO phase offset[15:8] 0x36 5 FRAME FTW acknowledge FRAME FTW request 4 1 Update FTW acknowledge Update FTW request I phase adjust[7:0] I Phase Adj LSB 0x38 0 [7:0] I Phase Adj MSB Q Phase Adj LSB 0x39 0x3A [1:0] [7:0] I p
AD9125 Register Name I Aux DAC Control Address (Hex) 0x43 Bits 7 Name I aux DAC sign 6 I aux DAC current direction I aux DAC sleep I Aux DAC[9:8] Q DAC FS adjust[7:0] Q DAC FS Adjust 0x44 5 [1:0] [7:0] Q DAC Control 0x45 7 Q DAC sleep Aux DAC Q Data 0x46 [1:0] [7:0] Q DAC FS adjust[9:8] Q aux DAC[7:0] Q Aux DAC Control 0x47 7 Q aux DAC sign 6 Q aux DAC current direction Die Temp Range Control 0x48 5 Q aux DAC sleep [1:0] [6:4] Q aux DAC[9:8] FS current[2:0] [3:1] Reference curr
AD9125 Register Name SED Control 1 Address (Hex) 0x67 Bits 7 Name SED compare enable 5 Sample error detected 3 Autoclear enable 1 Compare fail Compare I0 LSBs 0x68 0 [7:0] Compare pass Compare Value I0[7:0] Compare I0 MSBs Compare Q0 LSBs 0x69 0x6A [7:0] [7:0] Compare Value I0[15:8] Compare Value Q0[7:0] Compare Q0 MSBs 0x6B [7:0] Compare I1 LSBs 0x6C [7:0] Compare Value Q0[15:8] Compare Value I1[7:0] Compare I1 MSBs 0x6D [7:0] Compare Value I1[15:8] Compare Q1 LSBs 0x6E [7:0
AD9125 CMOS INPUT DATA PORTS The AD9125 input data port consists of a data clock (DCI), data bus, and FRAME signal. The data port can be configured to operate in three modes: dual-word mode, word mode, and byte mode. In dual-word mode, I and Q data is received simultaneously on two 16-pin buses. One bus receives I datapath input words, and the other bus receives Q datapath input words. In word mode, one 16-pin bus is used to receive interleaved I and Q input words.
AD9125 The data interface timing can be verified by using the sample error detection (SED) circuitry. See the Interface Timing Validation section for details. INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 45. The sampling point of the data bus occurs on the falling edge of the DCI signal and has an uncertainty of 2.1 ns, as illustrated by the sampling interval shown in Figure 45. The D[31:0] and FRAME signals must be valid throughout this sampling interval.
AD9125 The operation of the FRAME initiated FIFO reset depends on the synchronization mode chosen. When synchronization is disabled or when the device is configured for data rate mode synchronization, the FRAME strobe initiates a relative FIFO reset. When FIFO mode synchronization is chosen, the FRAME strobe initiates an absolute FIFO reset. More details on the synchronization function can be found in the Multichip Synchronization section.
AD9125 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band interpolation filters, a quadrature modulator with a fine resolution NCO, a phase and offset adjustment block, and an inverse sinc filter. Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 51. The shape of the filter response is identical in each of the four modes.
AD9125 Figure 52 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection, not by the pass-band flatness. Table 17 shows the pass-band flatness and stop-band rejection that the HB1 filter supports at different bandwidths. Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 53 and Figure 54. The shape of the filter response is identical in each of the eight modes.
AD9125 Half-Band Filter 3 (HB3) Table 18 summarizes the HB2 and HB3 modes. HB3 has eight modes of operation that function the same as HB2. The primary difference between HB2 and HB3 is the filter bandwidths. Table 18. HB2 and HB3 Filter Mode Summary fCENTER DC fIN/4 fIN/2 3fIN/4 fIN 5fIN/4 6fIN/4 7fIN/4 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex Figure 56 shows the pass-band filter response for HB3.
AD9125 NCO MODULATION DATAPATH CONFIGURATION The digital quadrature modulator makes use of a numerically controlled oscillator, a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 57.
AD9125 DETERMINING INTERPOLATION FILTER MODES HB1, HB2, AND HB3 Table 21 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required.
AD9125 DATAPATH CONFIGURATION EXAMPLE 4× Interpolation with NCO 8× Interpolation Without NCO Given the following conditions, the desired 140 MHz of bandwidth is 56% of fDATA: Given the following conditions, the desired 75 MHz of bandwidth is 75% of fDATA: • • • • fDATA = 100 MSPS 8× interpolation fBW = 75 MHz fCENTER = 100 MHz fDATA = 250 MSPS 4× interpolation fBW = 140 MHz fCENTER = 175 MHz As shown in Figure 58, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 − 2(0.7 − 0.6) = 0.6.
AD9125 DATA RATES VS. INTERPOLATION MODES Table 23 summarizes the maximum bus speed (fBUS), the supported input data rates, and the signal bandwidths for various combinations of bus width modes and interpolation rates. The maximum bus speed in any mode is 250 MHz. The maximum DAC update rate (fDAC) in any mode is 1000 MHz. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filter (HB1, HB2, or HB3) selected.
AD9125 The Q phase adjust bits (Bits[9:0]) work in a similar fashion. When the Q phase adjust[9:0]) is set to 1000000000, the Q DAC output moves approximately 1.75° away from the I DAC output, creating an angle of 91.75° between the channels. When the Q phase adjust[9:0] is set to 0111111111, the Q DAC output moves approximately 1.75° toward the I DAC output, creating an angle of 88.25° between the channels.
AD9125 DAC INPUT CLOCK CONFIGURATIONS DAC INPUT CLOCK CONFIGURATIONS The AD9125 DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip phased-locked loop (PLL) that accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which can be used to generate all the internal clocks required by the DAC.
AD9125 PLL Settings Manual VCO Band Select There are three settings for the PLL circuitry that should be programmed to their nominal values. Table 24 lists the recommended PLL settings for these parameters. The device also has a manual band select mode (PLL manual enable, Register 0x0A, Bit 6 = 1) that allows the user to select the VCO tuning band. When in manual mode, the VCO band is set directly with the value written to the manual VCO band, (Register 0x0A, Bits[5:0]).
AD9125 ANALOG OUTPUTS Figure 66 shows a simplified block diagram of the transmit path DACs. The DAC core consists of a current source array, a switch core, a digital control logic, and a full-scale output current control. The DAC full-scale output current (IOUTFS) is nominally 20 mA. The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC.
AD9125 IOUT1P VIP + –60 10mA 20mA 30mA –65 –70 IMD (dBc) Figure 68 shows the most basic DAC output circuitry. A pair of resistors, RO, is used to convert each of the complementary output currents to a differential voltage output, VOUT. Because the current outputs of the DAC are high impedance, the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 69 illustrates the output voltage waveforms. RO –75 –80 VOUTI RO VIN – –85 –90 0 IOUT2P 0.
AD9125 Interfacing to Modulators DRIVING THE ADL5375-15 The AD9125 interfaces to the ADL537x family of modulators with a minimal number of components. An example of the recommended interface circuitry is shown in Figure 73. The ADL5375-15 is the version of the ADL5375 that offers an input baseband bias levels of 1500 mV. Because the ADL5375-15 requires a 1500 mV dc bias, it requires a slightly more complex interface than most other Analog Devices, Inc., modulators.
AD9125 DEVICE POWER DISSIPATION The AD9125 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. 1800 The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 57 mA (188 mW) when the full-scale current of the I and Q DACs is set to the nominal value of 20 mA.
AD9125 300 TEMPERATURE SENSOR The AD9125 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed through Register 0x49 and Register 0x4A. The temperature of the die can be calculated by 250 POWER (mW) 200 150 TDIE = 100 88 where TDIE is the die temperature in oC. The temperature accuracy is ±5oC typical.
AD9125 MULTICHIP SYNCHRONIZATION Multiple devices are considered synchronized to each other when the state of the clock generation state machine is identical for all parts and when time aligned data is being read from the FIFOs of all parts simultaneously. Devices are considered synchronized to a system clock when there is a constant, known relationship among the clock generation state machine, the data being read from the FIFO, and a particular clock edge of the system clock.
AD9125 tSKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) tSU_DCI tH_DCI 09016-050 DCI(2) FRAME(2) Figure 82. Timing Diagram Required for Synchronizing Devices DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAME SAMPLE RATE CLOCK DCI LOW SKEW CLOCK DRIVER MATCHED LENGTH TRACES DACCLKP/ DACCLKN REFCLKP/ REFCLKN SYNC CLOCK IOUT1P/ IOUT1N FRAME LOW SKEW CLOCK DRIVER IOUT2P/ IOUT2N DCI 09016-051 FPGA Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock Rev.
AD9125 SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock, a separate REFCLK input signal is required for synchronization. To synchronize devices, the DACCLK signal and the REFCLK signal must be distributed with low skew to all of the devices being synchronized. If the devices need to be synchronized to a master clock, then use the master clock directly for generating the REFCLK input (see Figure 83).
AD9125 FIFO RATE MODE SYNCHRONIZATION The Procedure for FIFO Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the REFCLK and DACCLK signals are applied to all of the devices. The procedure must be carried out on each individual device. Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock To synchronize all devices, 2. 3.
AD9125 ADDITIONAL SYNCHRONIZATION FEATURES The synchronization logic incorporates additional features that provide means for querying the status of the synchronization, improving the robustness of the synchronization, and enabling a one-shot synchronization mode. These features are detailed in the Sync Status Bits and Timing Optimization sections. Sync Status Bits When the sync locked bit (Register 0x12, Bit 6) is set, it indicates that the synchronization logic has reached alignment.
AD9125 INTERRUPT REQUEST OPERATION The AD9125 provides an interrupt request output signal (on Pin 7, IRQ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device. This pin can be tied to the interrupt pins of other devices with open-drain outputs to wire-OR these pins together.
AD9125 INTERFACE TIMING VALIDATION The AD9125 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values, which are loaded into registers through the SPI port. Differences between these values are detected and stored. Options are available for customizing SED test sequencing and error handling.
AD9125 EXAMPLE START-UP ROUTINE Start-Up Sequence There are certain sequences that should be followed to ensure reliable startup of the AD9125. The following procedure sets the power clock and register write sequencing for reliable device start-up: The example start-up routine assumes the following device configuration: 1. • • • • • • • • • 2. 3. 4. fDATA = 122.88 MSPS Interpolation = 4×, using HB1 = 10 and HB2 = 010010 Input data = baseband data fOUT = 140 MHz fREFCLK = 122.
AD9125 OUTLINE DIMENSIONS 10.00 BSC SQ 0.60 0.42 0.24 0.60 0.42 0.24 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.75 BSC SQ 0.50 BSC 6.15 6.00 SQ 5.85 EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 12° MAX 19 8.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.23 0.18 18 37 36 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9125 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09016-0-6/10(0) Rev.