Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 64 VQ

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Dual Analog-to-Digital Converter

AD9204

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700 www.analog.com

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

61.3 dBFS at 9.7 MHz input

61.0 dBFS at 200 MHz input

SFDR

75 dBc at 9.7 MHz input

73 dBc at 200 MHz input

Low power

30 mW per channel at 20 MSPS

63 mW per channel at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

DNL = ±0.11 LSB

Serial port control options

Scalable analog input: 1 V p-p to 2 V p-p differential

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data

alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Ultrasound

Radar/LIDAR

PET/SPECT imaging

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

ORA

D0A

D9A

DCOA

DRVDD

ORB

D9B

D0B

DCOB

SDIOGND

DD SCLK

SPI

PROGRAMMING DATA

PDWN DFSCLK+ CLK–

MODE

CONTROLS

DCS

DUTY CYCLE

STABILIZER

SYNC

DIVIDE

1TO 8

OEB

CSB

REF

SELECT

ADC

CMOS

OUTPUT BUFFER

ADC

CMOS

OUTPUT BUFFER

AD9204

08122-001

MUX OPTION

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9204 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting,

internal clock divider, power-down, DCO/DATA timing

and offset adjustments, and voltage reference modes.

4. The AD9204 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9268 16-bit

ADC, the AD9251 and AD9258 14-bit ADCs, and the

AD9231 12-bit ADC, enabling a simple migration path

between 10-bit and 16-bit converters sampling from

20 MSPS to 125 MSPS.

Summary of content (36 pages)

PAGE 1
0-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.
PAGE 2
AD9204 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 22 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23 Functional Block Diagram ..............................................................
PAGE 3
AD9204 GENERAL DESCRIPTION The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
PAGE 4
AD9204 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 MATCHING CHARACTERISTICS Offset Error Gain Error1 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.
PAGE 5
AD9204 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.
PAGE 6
AD9204 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3.
PAGE 7
AD9204 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4.
PAGE 8
AD9204 TIMING SPECIFICATIONS Table 5.
PAGE 9
AD9204 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND D0A/D0B Through D13A/D13B to AGND DCOA/DCOB to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.
PAGE 10
AD9204 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9204 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D9A (MSB) D8A D7A D6A D5A DRVDD D4A D3A D2A D1A NOTES 1. NC = NO CONNECT 2.
PAGE 11
AD9204 Pin No. 49, 50, 53, 54, 59, 60, 63, 64 51, 52 55 56 57 58 61, 62 Mnemonic AVDD VIN+A, VIN−A VREF SENSE VCM RBIAS VIN−B, VIN+B Description 1.8 V Analog Supply Pins. Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev.
PAGE 12
AD9204 TYPICAL PERFORMANCE CHARACTERISTICS AD9204-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –20 –40 –60 –80 –100 –60 –80 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 Figure 6. AD9204-80 Single-Tone FFT with fIN = 9.7 MHz Figure 9. AD9204-80 Single-Tone FFT with fIN = 30.5 MHz 0 0 80MSPS 70.3MHz @ –1dBFS SNR = 60.4dB (61.
PAGE 13
AD9204 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 85 90 80 SFDR (dBc) SFDRFS 70 75 SNR/SFDR (dBc/dBFS) SNR/SFDR (dBFS/dBc) 80 70 65 SNR (dBFS) 60 SNRFS 60 50 40 SFDR 30 SNR 20 55 50 100 150 AIN FREQUENCY (MHz) 200 0 –60 –30 –40 –20 INPUT AMPLITUDE (dBc) –10 0 Figure 15. AD9204-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7MHz Figure 12. AD9204-80 SNR/SFDR vs.
PAGE 14
AD9204 AD9204-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 65MSPS 9.7MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) SFDR = 83.1dBc –10 SFDR/IMD3 (dBFS/dBc) AMPLITUDE (dB) –20 –40 –60 –80 –30 –50 SFDR (dBc) IMD3 (dBc) –70 SFDR (dBFS) –90 –100 5 10 15 20 FREQUENCY (MHz) 25 30 08122-030 0 –110 –60 Figure 18. AD9204-65 Single-Tone FFT with fIN = 9.
PAGE 15
AD9204 AD9204-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 90 0 40MSPS 9.7MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) SFDR = 82.0dBc SFDRFS 80 70 SNR/SFDR (dBc/dBFS) AMPLITUDE (dB) –20 –40 –60 –80 SNRFS 60 50 40 SFDR 30 SNR 20 –100 0 5 10 FREQUENCY (MHz) 15 20 0 –60 08122-028 –120 Figure 23. AD9204-40 Single-Tone FFT with fIN = 9.7 MHz 40MSPS 30.5MHz @ –1dBFS SNR = 60.6dB (61.
PAGE 16
AD9204 AD9204-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 90 20MSPS 9.7MHz @ –1dBFS SNR = 60.6dBFS (61.6dBFS) SFDR = 81.3dBc SFDR (dBFS) 80 70 SNR/SFDR (dBc/dBFS) AMPLITUDE (dB) –20 –40 –60 –80 SNR (dBFS) 60 50 SFDR (dBc) 40 SNR (dBc) 30 20 –100 0 2 4 6 FREQUENCY (MHz) 8 10 0 –60 08122-024 –120 Figure 26. AD9204-20 Single-Tone FFT with fIN = 9.7 MHz 20MSPS 30.
PAGE 17
AD9204 EQUIVALENT CIRCUITS DRVDD AVDD 08122-042 08122-039 VIN±x Figure 29. Equivalent Analog Input Circuit Figure 32. Equivalent Digital Output Circuit 5Ω CLK+ 15kΩ 0.9V 15kΩ DRVDD 5Ω CLK– 350Ω 30kΩ 08122-040 08122-043 SCLK/DFS, SYNC, OEB, AND PDWN Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 30. Equivalent Clock Input Circuit AVDD AVDD DRVDD 30kΩ SDIO/DCS 350Ω RBIAS AND VCM 375Ω 08122-041 08122-044 30kΩ Figure 34.
PAGE 18
AD9204 DRVDD AVDD AVDD 30kΩ 375Ω VREF 08122-045 7.5kΩ Figure 35. Equivalent CSB Input Circuit Figure 37. Equivalent VREF Circuit AVDD 375Ω 08122-046 SENSE Figure 36. Equivalent SENSE Circuit Rev.
PAGE 19
AD9204 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The analog input to the AD9204 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.
PAGE 20
AD9204 The analog inputs of the AD9204 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 39 and Figure 40.
PAGE 21
AD9204 10µF AVDD 1kΩ A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 43 shows a typical single-ended input configuration. 1V p-p R 0.1µF ADC C 1kΩ 10µF VIN+x 1kΩ AVDD R VIN–x 1kΩ Figure 43. Single-Ended Input Configuration 0.1µF 0.
PAGE 22
AD9204 Internal Reference Connection A comparator within the AD9204 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 46), setting VREF to 1.0 V.
PAGE 23
AD9204 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 48 shows the typical drift characteristics of the internal reference in 1.0 V mode. The AD9204 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
PAGE 24
AD9204 If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. CLK+ 0.1µF 50kΩ 50kΩ AD951x PECL DRIVER 240Ω 100Ω 0.1µF ADC CLK– 08122-019 CLOCK INPUT 0.1µF 240Ω Figure 52.
PAGE 25
AD9204 Jitter Considerations POWER DISSIPATION AND STANDBY MODE High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by As shown in Figure 57, the analog core power dissipated by the AD9204 is proportional to its sample rate.
PAGE 26
AD9204 The AD9204 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2.2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9204 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
PAGE 27
AD9204 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9204 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9204 is included. Various output test options are also provided to place predictable values on the outputs of the AD9204. generator, Bit 2 (BIST INIT) of Register 0x0E.
PAGE 28
AD9204 CHANNEL/CHIP SYNCHRONIZATION The AD9204 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence.
PAGE 29
AD9204 SERIAL PORT INTERFACE (SPI) The AD9204 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 30
AD9204 Table 15. Mode Selection HARDWARE INTERFACE The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9204. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers.
PAGE 31
AD9204 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 17) has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); the program registers (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 and Address 0x101).
PAGE 32
AD9204 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17.
PAGE 33
AD9204 Addr (Hex) 0x0D Register Name Test mode (local) Bit 7 (MSB) Bit 6 User test mode (local) 00 = single 01 = alternate 10 = single once 11 = alternate once 0x0E BIST enable Open 0x10 0x14 Offset adjust (local) Output mode 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 00 = 3.3 V CMOS Output mux Output Open Output 10 = 1.8 V CMOS enable disable invert (interleaved) (local) (local) 0x15 OUTPUT_ADJUST 1.
PAGE 34
AD9204 Bit 1 B9 Bit 0 (LSB) B8 Default Value (Hex) 0x00 Open Open B0 0x00 Open Open Open OR output enable (local) 0x01 Open Open Open Open 0 = ADC A 1 = ADC B (local) Ch A = 0x00 Ch B = 0x01 Open Open Open 0x01 Open Enable GCLK detect Clock divider sync enable Open Master sync enable Open Clock divider next sync only Run GCLK Disable SDIO pulldown 0x88 Addr (Hex) 0x1C Register Name USER_PATT2_MSB Bit 7 (MSB) B15 Bit 6 B14 Bit 5 B13 Bit 4 B12 Bit 3 B11 Bit 2 B10 0x24 MI
PAGE 35
AD9204 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9204 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9204, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V to 3.
PAGE 36
AD9204 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 49 PIN 1 INDICATOR 1 PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 33 32 16 17 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 6.35 6.20 SQ 6.05 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 091707-C 8.