Datasheet

Data Sheet AD9212
Rev. E | Page 11 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND
PIN 1
INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D – G
D + G
D – F
D + F
D – E
D + E
DCO–
DCO+
FCO–
FCO+
D – D
D + D
D – C
D + C
D – B
D + B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VIN + F VIN – F AVDD VIN – E VIN + E AVDD REFT REFB VREF SENSE RBIAS VIN +
D
VIN – D AVDD VIN – C VIN +
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD
VIN + G
VIN – G
AVDD
VIN – H
VIN + H
AVDD
AVDD
CLK–
CLK+
AVDD
AVDD
DRGND
DRVDD
D – H
D + H
AVDD
VIN + B
VIN – B
AVDD
VIN – A
VIN + A
AVDD
PDWN
CSB
SDIO/ODM
SCLK/DTP
AVDD
DRGND
DRVDD
D + A
D – A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9212
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
05968-005
Figure 5. 64-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
0 AGND Analog Ground (Exposed Paddle)
1, 4, 7, 8, 11,
12, 37, 42, 45,
48, 51, 59, 62
AVDD 1.8 V Analog Supply
13, 36 DRGND Digital Output Driver Ground
14, 35 DRVDD 1.8 V Digital Output Driver Supply
2 VIN + G ADC G Analog Input True
3 VIN − G ADC G Analog Input Complement
5 VIN − H ADC H Analog Input Complement
6 VIN + H ADC H Analog Input True
9 CLK− Input Clock Complement
10 CLK+ Input Clock True
15 D − H ADC H Digital Output Complement
16 D + H ADC H Digital Output True
17 D − G ADC G Digital Output Complement
18 D + G ADC G Digital Output True
19 D − F ADC F Digital Output Complement
20 D + F ADC F Digital Output True
21 D − E ADC E Digital Output Complement
22 D + E ADC E Digital Output True
23 DCO− Data Clock Digital Output Complement
24 DCO+ Data Clock Digital Output True
25 FCO− Frame Clock Digital Output Complement
26 FCO+ Frame Clock Digital Output True
27 D − D ADC D Digital Output Complement
28 D + D ADC D Digital Output True
29 D − C ADC C Digital Output Complement
30 D + C ADC C Digital Output True
31 D − B ADC B Digital Output Complement