Datasheet

Data Sheet AD9212
Rev. E | Page 29 of 56
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
that is nominally equal to 10.0 kΩ between the RBIAS pin and
ground. The resistor current is derived on chip and sets the
AVDD current of the ADC to a nominal 390 mA at 65 MSPS.
Therefore, it is imperative that at least a 1% tolerance on this
resistor be used to achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9212. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input
span of 2 V p-p. VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
improve accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low-ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9212. The recommended capacitor values and
configurations for the AD9212 reference pin are shown in
Figure 63.
Table 13. Reference Settings
Selected
Mode
SENSE
Voltage
Resulting
VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD N/A
2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V 1.0 2.0
Internal Reference Operation
A comparator within the AD9212 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 63), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9212 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 65
depicts how the internal reference voltage is affected by loading.
1µF 0.1µF
VREF
SENSE
0.5V
REFT
0.1µF
0.1µF
4.7µF
0.1µF
REFB
SELECT
LOGIC
ADC
CORE
+
VIN – x
VIN + x
05968-031
Figure 63. Internal Reference Configuration
1µF
1
0.1µF
1
VREF
SENSE
AVDD
0.5V
REFT
0.1µF
0.1µF 4.7µF
0.1µF
REFB
SELECT
LOGIC
ADC
CORE
+
VIN – x
VIN + x
EXTERNAL
REFERENCE
1
OPTIONAL.
0
5968-032
Figure 64. External Reference Operation
01.00.5 2.01.5 3.02.5 3.5
VREF ERROR (%)
CURRENT LOAD (mA)
05968-087
–30
–5
–10
–15
–20
–25
5
0
Figure 65. VREF Accuracy vs. Load