Datasheet

Data Sheet AD9212
Rev. E | Page 7 of 56
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9212-40 AD9212-65
Parameter
1
Temp
Min Typ Max Min Typ Max Unit
CLOCK
2
Maximum Clock Rate Full 40 65 MSPS
Minimum Clock Rate Full 10 10 MSPS
Clock Pulse Width High (t
EH
) Full 12.5 7.7 ns
Clock Pulse Width Low (t
EL
) Full 12.5 7.7 ns
OUTPUT PARAMETERS
2, 3
Propagation Delay (t
PD
) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns
Rise Time (t
R
) (20% to 80%) Full 300 300 ps
Fall Time (t
F
) (20% to 80%) Full 300 300 ps
FCO Propagation Delay (t
FCO
) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns
DCO Propagation Delay (t
CPD
)
4
Full t
FCO
+
(t
SAMPLE
/20)
t
FCO
+
(t
SAMPLE
/20)
ns
DCO to Data Delay (t
DATA
)
4
Full (t
SAMPLE
/20) − 300 (t
SAMPLE
/20) (t
SAMPLE
/20) + 300 (t
SAMPLE
/20) − 300 (t
SAMPLE
/20) (t
SAMPLE
/20) + 300 ps
DCO to FCO Delay (t
FRAME
)
4
Full (t
SAMPLE
/20) − 300 (t
SAMPLE
/20) (t
SAMPLE
/20) + 300 (t
SAMPLE
/20) − 300 (t
SAMPLE
/20) (t
SAMPLE
/20) + 300 ps
Data-to-Data Skew
(t
DATA-MAX
− t
DATA-MIN
)
Full ±50 ±200 ±50 ±200 ps
Wake-Up Time (Standby) 25°C 600 600 ns
Wake-Up Time (Power-Down) 25°C 375 375 μs
Pipeline Latency Full 8 8 CLK
cycles
APERTURE
Aperture Delay (t
A
) 25°C 750 750 ps
Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms
Out-of-Range Recovery Time 25°C 1 1 CLK
cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI interface.
3
Measurements were made using a part soldered to FR-4 material.
4
t
SAMPLE
/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.