FEATURES 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) ENOB = 9.8 bits SFDR = 80 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.
AD9212 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 23 Applications ....................................................................................... 1 Serial Port Interface (SPI) .............................................................. 31 General Description ..............................................................
Data Sheet AD9212 REVISION HISTORY 12/11—Rev. D to Rev. E Changes to Output Signals Section and Figure 70......................37 Changed Default Operation and Jumper Selection Settings Section ..............................................................................................38 Added Endnote 2 in Ordering Guide ...........................................56 5/10—Rev. C to Rev. D Deleted LFCSP CP-64-3 Package .....................................
AD9212 Data Sheet SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.
Data Sheet AD9212 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.
AD9212 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3.
Data Sheet AD9212 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4.
AD9212 Data Sheet TIMING DIAGRAMS N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x MSB N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D8 N–8 D7 N–8 D6 N–8 D5 N–8 05968-002 D+x Figure 2. 10-Bit Data Serial Stream (Default), MSB First N–1 VIN ± x tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D+x Figure 3.
Data Sheet AD9212 N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x D0 N–9 D1 N–9 D2 N–9 D3 N–9 D4 N–9 D5 N–9 D6 N–9 D7 N–9 D8 N–9 LSB N–8 D0 N–8 D1 N–8 D2 N–8 05968-004 LSB N–9 D+x Figure 4. 10-Bit Data Serial Stream, LSB First Rev.
AD9212 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− VIN + x, VIN − x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Table 6. With Respect To Rating AGND DRGND DRGND DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +2.
Data Sheet AD9212 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VIN + F VIN – F AVDD VIN – E VIN + E AVDD REFT REFB VREF SENSE RBIAS VIN + D VIN – D AVDD VIN – C VIN + C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9212 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD VIN + B VIN – B AVDD VIN – A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D–A NOTES 1.
AD9212 Pin No.
Data Sheet AD9212 EQUIVALENT CIRCUITS DRVDD V V D–x D+x 05968-006 V DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit CLK+ V 05968-009 VIN ± x 10Ω 10kΩ 1.25V 10kΩ SCLK/DTP OR PDWN 10Ω 1kΩ CLK– 05968-010 05968-007 30kΩ Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit RBIAS 30kΩ 05968-011 350Ω 05968-008 SDIO/ODM 100Ω Figure 11. Equivalent RBIAS Circuit Figure 8.
AD9212 Data Sheet AVDD 70kΩ CSB 1kΩ 6kΩ Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1kΩ 05968-013 SENSE 05968-014 05968-012 VREF Figure 13. Equivalent SENSE Circuit Rev.
Data Sheet AD9212 TYPICAL PERFORMANCE CHARACTERISTICS 0 –40 –60 –80 0 10 15 20 FREQUENCY (MHz) 25 30 5 10 15 20 FREQUENCY (MHz) 0 25 30 AIN = –0.5dBFS SNR = 60.25dB ENOB = 9.66 SFDR = 72.45dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –40 –60 –80 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 –120 05968-038 0 Figure 16. Single-Tone 32k FFT with fIN = 19.7 MHz, AD9212-40 0 5 10 15 20 FREQUENCY (MHz) 25 30 Figure 19. Single-Tone 32k FFT with fIN = 70 MHz, AD9212-65 0 AIN = –0.
AD9212 Data Sheet 90 90 SFDR SFDR 85 85 80 SNR/SFDR (dB) 75 70 65 75 70 65 SNR 60 55 55 50 10 15 20 25 30 40 35 ENCODE RATE (MSPS) 50 10 20 30 40 50 05968-046 SNR 60 05968-043 SNR/SFDR (dB) 80 60 ENCODE RATE (MSPS) Figure 24. SNR/SFDR vs. fSAMPLE, fIN = 35 MHz, AD9212-65 Figure 21. SNR/SFDR vs. fSAMPLE, fIN = 10.
Data Sheet AD9212 100 0 AIN1 AND AIN2 = –7dBFS SFDR = 76.7dB IMD2 = 83.38dBc IMD3 = 77.21dBc 90 –20 80 AMPLITUDE (dBFS) SNR/SFDR (dB) 70 60 50 SFDR 40 30 70dB REFERENCE –40 –60 –80 SNR 20 –100 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 –120 Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9212-65 0 2 4 6 0 –20 80 AMPLITUDE (dBFS) SNR/SFDR (dB) 50 SFDR 40 70dB REFERENCE 30 18 20 AIN1 AND AIN2 = –7dBFS SFDR = 77.4dB IMD2 = 77.92dBc IMD3 = 76.
AD9212 Data Sheet 80 0.5 0.4 75 0.3 SFDR 0.2 INL (LSB) SNR/SFDR (dB) 70 65 SNR 60 0.1 0 –0.1 –0.2 –0.3 55 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 –0.5 05968-055 1 0 200 400 600 800 1000 CODE 05968-058 –0.4 50 Figure 36. INL, fIN = 2.3 MHz, AD9212-65 Figure 33. SNR/SFDR vs. fIN, AD9212-65 0.5 90 0.4 85 0.3 0.2 SFDR 75 DNL (LSB) SINAD/SFDR (dB) 80 70 65 SINAD 0.1 0 –0.1 –0.2 60 –0.3 55 –20 0 20 40 TEMPERATURE (°C) 60 80 –0.5 0 600 800 1000 Figure 37.
Data Sheet AD9212 2.5 0 0.096 LSB rms –1 –3 AMPLITUDE (dBFS) NUMBER OF HITS (Millions) –3dB BANDWIDTH = 325MHz –2 2.0 1.5 1.0 –4 –5 –6 –7 –8 0.5 –9 N–3 N–2 N–1 N CODE N+1 N+2 –11 05968-062 0 N+3 –60 –80 –100 0 5 10 15 20 FREQUENCY (MHz) 25 05968-063 AMPLITUDE (dBFS) –40 –120 100 150 200 250 300 350 400 450 500 Figure 41. Full Power Bandwidth vs. Frequency, AD9212-65 NPR = 51.13dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz –20 50 FREQUENCY (MHz) Figure 39.
AD9212 Data Sheet THEORY OF OPERATION The AD9212 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic.
Data Sheet AD9212 90 90 85 85 SFDR (dBc) SNR/SFDR (dB) 80 75 70 65 SNR (dB) 70 65 55 0.6 0.9 1.2 1.5 ANALOG INPUT COMMON-MODE VOLTAGE (V) 50 0.3 0.9 85 85 80 80 SNR/SFDR (dB) 90 75 SFDR (dBc) 70 65 1.5 SFDR 75 70 65 SNR SNR (dB) 60 55 55 0.9 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) 1.5 05968-066 60 0.6 1.5 Figure 45. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, AD9212-65 90 50 0.3 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 43. SNR/SFDR vs.
AD9212 Data Sheet ADT1-1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core.
Data Sheet AD9212 For optimum performance, the AD9212 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 51 shows the preferred method for clocking the AD9212. The low jitter clock source is converted from single-ended to differential using an RF transformer.
AD9212 Data Sheet Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 57 and Figure 58, the power dissipated by the AD9212 is proportional to its sample rate.
Data Sheet AD9212 By asserting the PDWN pin high, the AD9212 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9212 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths.
AD9212 EYE: ALL BITS 400 ULS: 12071/12071 EYE DIAGRAM VOLTAGE (mV) EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 –400 –500 –1.0ns –0.5ns 0ns 0.5ns 1.0ns 0 –100 –200 –300 80 80 70 70 60 50 40 30 20 500 –50ps 0ps 50ps 100ps 150ps 05968-030 –100ps EYE: ALL BITS 0ns 0.5ns 1.0ns 1.5ns –100ps –50ps 0ps 50ps 100ps 150ps 50 40 30 20 Figure 62.
Data Sheet AD9212 Two output clocks are provided to assist in capturing data from the AD9212. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the AD9212 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. Table 9.
AD9212 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 12-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial stream to test the device’s compatibility with lower and higher resolution systems.
Data Sheet AD9212 CSB Pin VIN + x The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. VIN – x REFT 0.1µF ADC CORE 0.1µF 4.7µF REFB RBIAS Pin 0.1µF VREF 1µF 0.1µF 0.5V SELECT LOGIC SENSE 05968-031 To set the internal core bias current of the ADC, place a resistor that is nominally equal to 10.0 kΩ between the RBIAS pin and ground.
AD9212 Data Sheet 0.02 External Reference Operation –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 –0.14 –0.16 –0.18 –40 –20 0 20 40 TEMPERATURE (°C) Figure 66. Typical VREF Drift Rev. E | Page 30 of 56 60 80 05968-088 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load.
Data Sheet AD9212 SERIAL PORT INTERFACE (SPI) The AD9212 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER 05968-059 Data Sheet VOH (V) AD9212 Figure 67. SDIO Pin Loading tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 05968-033 SDIO DON’T CARE DON’T CARE Figure 68. Serial Timing Details Table 15.
Data Sheet AD9212 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22).
AD9212 Data Sheet Table 16. Memory Map Register1 Addr.
Data Sheet AD9212 Addr. (Hex) 14 Parameter Name output_mode (MSB) Bit 7 X 15 output_adjust X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power, (IEEE 1596.
AD9212 Data Sheet APPLICATIONS INFORMATION DESIGN GUIDELINES Exposed Paddle Thermal Heat Slug Recommendations Before starting design and layout of the AD9212 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.
Data Sheet AD9212 EVALUATION BOARD board individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed.
AD9212 Data Sheet A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 Ω resistors, and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 μF capacitor, and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation.
Data Sheet AD9212 To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. Remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. Remove L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 on the AD8334 analog outputs.
Rev. E | Page 40 of 56 Channel A P101 Figure 74. Evaluation Board Schematic, DUT Analog Inputs VGA Input Connection R115 64.9Ω R114 0Ω−DNP INH2 R102 64.9Ω R101 0Ω−DNP DNP: DO NOT POPULATE. Ain P103 Channel B Ain INH1 VGA Input Connection Ain DNP P104 Ain 0Ω R117 R103 0Ω C109 0.1µF C108 0.1µF AVDD_DUT R116 0Ω FB104 10Ω E102 R125 1KΩ R126 1kΩ 1 R113 3 2 C114 0.1µF 0Ω−DNP R124 4 5 6 R118 0Ω−DNP C107 0.
Rev. E | Page 41 of 56 Ain Figure 75. Evaluation Board Schematic, DUT Analog Inputs (Continued) R218 64.9Ω R217 0Ω−DNP Ain VGA Input Connection INH6 R202 64.9Ω R201 0Ω−DNP DNP P204 Ain DNP: DO NOT POPULATE. P203 Channel F P201 Channel E Ain VGA Input Connection INH5 R203 0Ω R212 1kΩ 1kΩ R211 CM5 1 CH_E CM5 CH_E E202 C209 0.1µF R232 1kΩ R231 1kΩ CM6 1 CH_F CM6 C208 0.1µF CH_F E201 C202 0.1µF C201 0.
Rev. E | Page 42 of 56 16 D+H D−H DRVDD DRGND AVDD D+C VIN−D D−C VIN+D D+D RBIAS FCO+ D−D FCO− DCO+ DCO− AVDD D+E VIN+E VIN−E D−E D+F AVDD D−F VIN+F VIN−F D+G D−G 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CHB CHD CHD FCO FCO Figure 76. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface CHC CHC C305 0.1µF VOUT CHB R308 470kΩ D−B 31 R310 10kΩ R311 DNP R313 DNP C307 1µF R312 DNP VREF_DUT Remove C214 when using external Vref C306 0.
Enc Figure 77. Evaluation Board Schematic, Clock Circuitry Rev. E | Page 43 of 56 DNP: DO NOT POPULATE. R405 0Ω 0Ω 1 6 C411 0.1µF R418 0Ω S7 CR401 S8 S6 HSMS-2812-TR1G S9 8 5 7 S10 9 4 VREF T401 S10 10 2 1 SIGNAL=DNC;27,28 S5 S4 S3 S2 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 S9 11 3 E401 GND_PAD AD9515BCPZ S8 12 R416 R417 0Ω SYNCB CLKB CLK U401 S7 13 0Ω R415 R413 10kΩ 5 3 2 AVDD_3.3V S6 14 C403 0.1µF OPT_CLK R407 0Ω R412 DNP DNP R411 49.9Ω DNP R414 4.
1 2 EXT VG CW GND VG12 EXT VG L502 120nH Variable Gain Circuit (0−1.0V DC) VG12 External Variable Gain Drive Rev. E | Page 44 of 56 R508 274Ω INH1 C524 0.1µF 16 15 INH3 LMD3 VIP4 LON4 LOP4 COM4X LMD1 LMD4 INH1 INH4 COM1 COM4 COM3 L501 120nH 0.1µF C513 27 26 24 23 20 19 18 R509 274Ω GND VG34 External Variable Gain Drive Figure 78. Evaluation Board Schematic, Optional DUT Analog Input Drive C532 0.1µF VIN4 25 VG34 AVDD_5V 22 17 C527 0.
1 CW C615 0.018µF L602 120nH GND VG56 Variable Gain Circuit (0−1.0V DC) VG56 External Variable Gain Drive Rev. E | Page 45 of 56 R608 274Ω INH5 C624 0.1µF 16 15 INH3 LMD3 COM3X LON3 LOP3 VPS4 VIN4 LOP4 VIP4 COM4X LON4 LMD4 INH1 INH4 COM1 COM4 COM3 L601 120nH 0.1µF C613 AVDD_5V 30 27 26 25 24 20 19 R609 274Ω 18 17 VG78 External Variable Gain Drive Figure 79. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) C632 0.
4 OPTIONAL GREEN Rev. E | Page 46 of 56 Figure 80. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry ADP3339AKCZ−1.8-RL GND 1 2 OUT 4 OUT 4 E701 J702 1 0Ω−DNP R704 C717 1µF L706 10µH C715 1µF L705 10µH 0Ω−DNP R703 DUT_DRVDD DUT_AVDD 0Ω−DNP R705 R711 10kΩ C721 1µF PWR_IN C719 1µF PWR_IN R714 10kΩ R715 10kΩ 3 IN IN GND ADP3339AKCZ−3.
AD9212 05968-079 Data Sheet Figure 81. Evaluation Board Layout, Primary Side Rev.
Data Sheet 05968-045 AD9212 Figure 82. Evaluation Board Layout, Ground Plane Rev.
AD9212 05968-046 Data Sheet Figure 83. Evaluation Board Layout, Power Plane Rev.
Data Sheet 05968-082 AD9212 Figure 84. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev.
Data Sheet AD9212 Table 17.
AD9212 Item 8 Qty per Board 8 9 1 10 9 11 16 12 4 13 Data Sheet Reference Designator C503, C514, C520, C526, C603, C614, C620, C626 C704 Device Capacitor Package 402 Value 22 pF, ceramic, NPO, 5% tol, 50 V Manufacturer Murata Manufacturer Part Number GRM1555C1H220JZ01D Capacitor 1206 ROHM Co., Ltd. TCA1C106M8R Capacitor 603 10 μF, tantalum, 16 V, 20% tol 1 μF, ceramic, X5R, 6.3 V, 10% tol Murata GRM188R61C105KA93D Capacitor 805 0.
Data Sheet Item 26 Qty per Board 32 27 1 28 9 29 Reference Designator L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 AD9212 Manufacturer Part Number NRC04Z0TRF Device Resistor Package 805 Value 0 Ω, 1/8 W, 5% tol Manufacturer NIC Components Corp. Oscillator SMT Clock oscillator, 65.00 MHz, 3.3 V, ±5% duty cycle Side-mount SMA for 0.
AD9212 Item 37 Qty per Board 8 38 Data Sheet Device Resistor Package 402 Value 499 Ω, 1/16 W, 1% tol 3 Reference Designator R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, 1% tol 39 1 R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol 40 41 1 1 R404 R309 Resistor Resistor 402 402 49.9 Ω, 1/16 W, 0.5% tol 4.
Data Sheet Item 55 Qty per Board 9 56 2 Reference Designator T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 57 2 58 59 60 AD9212 Device Transformer Package CD542 IC SOT-223 U501, U601 IC CP-64-3 1 1 1 U706 U705 U301 IC IC IC SOT-223 SOT-223 CP-64-3 61 1 U302 IC SOT-23 62 1 U401 IC 63 1 U702 IC 64 1 U703 IC 65 1 U701 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value ADT1-1WT+, 1:1 impedance ratio transformer ADP3339AKC-1.8-RL, 1.5 A, 1.
AD9212 Data Sheet OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 1 49 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.22 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 16 17 33 32 TOP VIEW 1.00 0.85 0.80 7.55 7.50 SQ 7.45 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.