Datasheet

AD9215 Data Sheet
Rev. B | Page 16 of 36
Table 7. Reference Configuration Summary
Selected Mode
External SENSE
Connection
Internal Op Amp
Configuration
Resulting VREF
(V)
Resulting Differential Span
(V p-p)
Externally Supplied Reference AVDD N/A N/A 2 × External Reference
Internal 0.5 V Reference VREF Voltage Follower (G = 1) 0.5 1.0
Programmed Variable
Reference
External Divider Noninverting (1 < G < 2) 0.5 × (1 + R2/R1) 2 × VREF
Internally Programmed 1 V
Reference
AGND to 0.2 V Internal Divider 1.0 2.0
Table 8. Digital Output Coding
Code
VIN+ − VIN− Input Span =
2 V p-p (V)
VIN+ − VIN− Input Span =
1 V p-p (V)
Digital Output Offset Binary
(D9••••••D0)
Digital Output Twos
Complement (D9••••••D0)
1023 1.000 0.500 11 1111 1111 01 1111 1111
512 0 0 10 0000 0000 00 0000 0000
511 −0.00195 −0.000978 01 1111 1111 11 1111 1111
0 −1.00 −0.5000 00 0000 0000 10 0000 0000
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
INPUT
) due only to aperture jitter (t
A
) can be
calculated with the following equation
SNR Degradation = 20 × log
10
[2 × π × f
INPUT
× t
A
]
In the equation, the rms aperture jitter, t
A
, represents the root-
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9215. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
I
DRVDD
= V
DRVDD
× C
LOAD
× f
CLOCK
× N
where N is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full-scale square wave at the Nyquist frequency, f
CLOCK
/2. In
practice, the DRVDD current is established by the average
number of output bits switching, which are determined by the
encode rate and the characteristics of the analog input signal.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in Fig-
ure 35 was taken with a 5 pF load on each output driver.
02874-A-075
15
35
30
25
20
40
1055 15 25 35 45 55 65 75 85 95
I
AVDD
(mA)
I
DRVDD
–1
1
3
5
7
9
11
13
15
f
SAMPLE
(MSPS)
AD9215-105 I
AVDD
AD9215-65/80 I
AVDD
I
DRVDD
Figure 35. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal opera-
tional mode.
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The