Datasheet

Data Sheet AD9215
Rev. B | Page 21 of 36
02874-A-041
C10
22µF
C4
10µF
C3
10µF
C25
10µF
C32
0.001µF
C33
0.1µF
C14
0.001µF
VDL
DRVDD AVDD
GND
GND
AVDD
DUT BYPASSING
CLOCK TIMING ADJUSTMENTS FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27
ANALOG BYPASSING DIGITAL BYPASSING
GND
DRVDD
C41 0.1µF
C2
22µF
C30
0.001µF
C31 0.1µF
C46
10µF
C34 0.1µF
C36 0.1µF
C38 0.001µF
C1 0.1µF
C47 0.1µF
C48 0.001µF
C49 0.001µF
C20
10µF
C37
0.1µF
C40
0.001µF
GND
GND
VAMP
VDL
C39 0.001µF
ENCX
CLK
ENC
ENCODE
R27 0Ω
R32 1kΩ
R23
0Ω
R37 25Ω
R22 0Ω
Rx DNP
R28 0Ω
E50
E51
ENC
VDL
VDL
VDL
E52 E53
E31 E35 E43 E44
GND
GND
GND
PWR
GND
CLKLAT/DAC
VDL
GND
VDL
GND
C43 0.1µF
R31 1kΩ
R20 1kΩ
R21 1kΩ
R24 1kΩ
R30 1kΩ
R29 50Ω
GND
J2
GND VDL
GND
1
1Y
U5
2Y
3Y 4Y
2 4 5 9
10
3
6
7 8
11
14
12 13
74VCX86
ENCX
1B
1A
2B
2A
3B
3A
4B
4A
DR
SCHEMATIC SHOWS TWO-GATE DELAY SETUP. FOR ONE DELAY REMOVE R22 AND R37 ATTACH Rx (Rx = 0Ω)
LATCH BYPASSING
Figure 43. LFCSP Evaluation Board Schematic, Clock Input