Datasheet

AD9215 Data Sheet
Rev. B | Page 28 of 36
02874-A-050
+
C27 10F
+
C25 10F
C24 0.1F
C26 0.1F
C37 0.001F
C38 0.001F
VDL
GND
U3/U4 BYPASSING
+
C20 10F
C36 0.1F
C39 0.001F
VCLK
GND
U5 BYPASSING
AVDD BYPASSING GND
AVDD
C48 0.1F
C34 0.1F
C35 0.001F
C49 0.001F
C51 0.1F
+
C50 10F
GNDGND
DUT BYPASSING
VCLK
+
C2 22F
VDL
+
C10 22F
DRVDD
+
C4 10F
AVDD
+
C3 22F
C46 0.1F
DRVDD
GND
DUT DRVDD BYPASSING
C21 0.1F
C19 0.001F
1A 1B
1Y
2A 2B
2Y
3A 3B
3Y
4A 4B
4Y
PWR GND
ENCODE
SCHEMATIC SHOWS 1-GATE DELAY SETUP FOR TWO-GATE DELAY REMOVE RESISTOR R52 ADD RESISTORS R38 AND R18
OPTIONAL EXTERNAL DATA READY
VCLK
DRX
DRX
DRX
ENCX
1 2
3
4 5
6
9
10
8
12 13
11 14 7
U5
74VCX86
CLKLAT/DAC
J3
GND
E52 E53
GND
GND
GND
AVDD
E51E50
GND
E44E43
VCLK
GND VCLK
ENCX
ENC
CLK
GND
VCLK
E36E35
GND
ENC
VCLK
J4
GNDGND
ENCODE FROM XOR FOR A BUFFERED ENCODE USE R37 FOR A DIRECT ENCODE USE R35
R40
50
R41 1k R42 1k
R39
1k
R26
1k
R2
1k
R43
1k
R52
0
R38
0
R18
0
R25
0
R35
0
R37
0
R14 50
C40
0.1F
C28
0.1F
Figure 52. TSSOP Evaluation Board Schematic, Clock Input