Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Product Highlights
- Revision History
- Specifications
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Equivalent Circuits
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Memory Map
- Evaluation Board
- Outline Dimensions

AD9219 Data Sheet
Rev. E | Page 26 of 56
100
50
0
–100ps 0ps 100ps
TIE JITTER HISTOGRAM (Hits)
500
–500
0
–1ns –0.5ns 0ns 0.5ns 1ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS
ULS: 10000/15600
05726-043
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
200
–200
0
–1ns –0.5ns 0ns 0.5ns 1ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS
ULS: 9600/15600
100
50
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
05726-044
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
100
50
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
200
400
–200
–400
0
–1ns –0.5ns 0ns 0.5ns 1ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS
ULS: 9599/15599
05726-042
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Ω Far Termination Only
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) − (VIN − x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D9 ... D0)
1023 +1.00 1111 1111 11
512 0.00 1000 0000 00
511 −0.001953 0111 1111 11
0 −1.00 0000 0000 00
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 10 bits
times the sample clock rate, with a maximum of 650 Mbps
(10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.