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Octal, 12-Bit, 40/50/65 MSPS

Serial LVDS 1.8 V A/D Converter

Data Sheet

AD9222

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

FEATURES

8 ADCs integrated into 1 package

114 mW ADC power per channel at 65 MSPS

SNR = 70 dB (to Nyquist)

ENOB = 11.3 bits

SFDR = 80 dBc

Excellent linearity: DNL = ±0.3 LSB (typical),

INL = ±0.4 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar IEEE 1596.3)

Data and frame clock outputs

325 MHz full-power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

Test equipment

GENERAL DESCRIPTION

The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to-

digital converter (ADC) with an on-chip sample-and-hold

circuit designed for low cost, low power, small size, and ease of

use. The product operates at a conversion rate of up to 65 MSPS

and is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock output (DCO)

for capturing data on the output and a frame clock output (FCO)

for signaling a new output byte are provided. Individual-channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

FUNCTIONAL BLOCK DIAGRAM

SERIAL

LVDS

REF

SELECT

AD9222

AGND

VIN – A

VIN + A

VIN – B

VIN + B

VIN – D

VIN + D

VIN – C

VIN + C

SENSE

VREF

AVDD DRVDD

PDWN

REFT

REFB

D – A

D + A

D – B

D + B

D – D

D + D

D – C

D + C

FCO –

FCO +

DCO +

DCO –

CLK+

DRGND

CLK–

SERIAL PORT

INTERFACE

CSB

SCLK/

DTP

SDIO/

ODM

RBIAS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

ADC

DATA RATE

MULTIPLIER

0.5V

SERIAL

LVDS

VIN – E

VIN + E

VIN – F

VIN + F

VIN – H

VIN + H

VIN – G

VIN + G

D – E

D + E

D – F

D + F

D – H

D + H

D – G

D + G

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

ADC

05967-001

Figure 1.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

The AD9222 is available in an RoHS compliant, 64-l e a d L F C S P. It i s

specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small,

space-saving package.

2. Low power of 114 mW/channel at 65 MSPS.

3. Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 390 MHz and supports

double data rate (DDR) operation.

4. User Flexibility. The SPI control offers a wide range of

flexible features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9212 (10-bit)

and AD9252 (14-bit).

Summary of content (60 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.
PAGE 2
AD9222 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 21 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 24 General Description .........................................................................
PAGE 3
Data Sheet AD9222 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.
PAGE 4
AD9222 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.
PAGE 5
Data Sheet AD9222 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3.
PAGE 6
AD9222 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. Min Full Full Full Full 40 Full Full Full Full Full 1.
PAGE 7
Data Sheet AD9222 TIMING DIAGRAMS N–1 tA VIN ± x N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D10 N–8 D+x 05967-002 D–x Figure 2.
PAGE 8
AD9222 Data Sheet N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x D0 N–9 D1 N–9 D2 N–9 D3 N–9 D4 N–9 D5 N–9 D6 N–9 D7 N–9 D8 N–9 D9 N–9 D10 N–9 LSB N–8 D0 N–8 05967-004 LSB N–9 D+x Figure 4. 12-Bit Data Serial Stream, LSB First Rev.
PAGE 9
Data Sheet AD9222 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− VIN + x, VIN − x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To Rating AGND DRGND DRGND DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.
PAGE 10
AD9222 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VIN + F VIN – F AVDD VIN – E VIN + E AVDD REFT REFB VREF SENSE RBIAS VIN + D VIN – D AVDD VIN – C VIN + C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9222 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD VIN + B VIN – B AVDD VIN – A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D–A NOTES 1.
PAGE 11
Data Sheet Pin No.
PAGE 12
AD9222 Data Sheet EQUIVALENT CIRCUITS DRVDD V V D– VIN ± x D+ V 05967-009 05967-006 V DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ SCLK/DTP AND PDWN 10Ω 1kΩ 30kΩ 05967-010 05967-007 CLK– Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit RBIAS 30kΩ 05967-011 350Ω 05967-008 SDIO/ODM 100Ω Figure 11. Equivalent RBIAS Circuit Figure 8.
PAGE 13
Data Sheet AD9222 AVDD 70kΩ CSB 1kΩ 6kΩ Figure 14. Equivalent VREF Circuit Figure 12. Equivalent CSB Input Circuit 1kΩ 05967-013 SENSE 05967-014 05967-012 VREF Figure 13. Equivalent SENSE Circuit Rev.
PAGE 14
AD9222 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS SNR = 70.79dB ENOB = 11.47 BITS SFDR = 84.71dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –80 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) –120 0 5 10 15 20 25 FREQUENCY (MHz) 05967-018 0 05967-015 –120 Figure 18. Single-Tone 32k FFT with fIN = 35 MHz, AD9222-50 Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-40 0 0 AIN = –0.5dBFS SNR = 70.32dB ENOB = 11.39 BITS SFDR = 84.28dBc AIN = –0.5dBFS SNR = 70.
PAGE 15
Data Sheet AD9222 0 0 AIN = –0.5dBFS SNR = 70.21dB ENOB = 11.31 BITS SFDR = 82.37dBc –40 –60 –80 –40 –60 –80 5 10 15 20 25 30 FREQUENCY (MHz) –120 05967-085 0 0 5 10 15 20 25 05967-088 –100 –100 –120 AIN = –0.5dBFS SNR = 68.67dB ENOB = 10.79 BITS SFDR = 71.49dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 30 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-65 Figure 24. Single-Tone 32k FFT with fIN = 120 MHz, AD9222-65 100 0 AIN = –0.
PAGE 16
AD9222 Data Sheet 100 90 95 80 SNR/SFDR (dB) SNR/SFDR (dB) 70 2V p-p, SFDR 90 85 80 75 70 60 80dB REFERENCE LINE 50 2V p-p, SFDR 40 2V p-p, SNR 30 20 2V p-p, SNR 65 15 20 25 30 35 40 45 50 55 60 65 ENCODE (MSPS) 0 –60 05967-089 60 10 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) 05967-091 10 Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9222-65 Figure 27. SNR/SFDR vs. fSAMPLE, fIN = 2.
PAGE 17
Data Sheet AD9222 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 89.87dB IMD2 = 96.07dBc IMD3 = 90.16dBc –20 AMPLITUDE (dBFS) –40 –60 –80 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) –120 05967-025 0 Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-40 0 5 10 15 20 25 FREQUENCY (MHz) Figure 36. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-50 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 77.24dB IMD2 = 91.66dBc IMD3 = 77.72dBc AIN1 AND AIN2 = –7dBFS SFDR = 79.
PAGE 18
AD9222 Data Sheet 90 90 85 85 2V p-p, SFDR SINAD/SFDR (dB) SNR/SFDR (dB) SFDR 80 75 SNR 70 80 75 70 2V p-p, SINAD 65 1 10 100 60 –40 05967-029 60 1000 ANALOG INPUT FREQUENCY (MHz) –20 0 20 40 60 05967-096 65 80 TEMPERATURE (°C) Figure 39. SNR/SFDR vs. fIN, AD9222-50 Figure 42. SINAD/SFDR vs. Temperature, fIN = 2.
PAGE 19
AD9222 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 CODE –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 35 40 CODE 05967-099 DNL (LSB) 1.0 05967-036 INL (LSB) Data Sheet Figure 48. DNL, fIN = 35 MHz, AD9222-65 Figure 45. INL, fIN = 2.3 MHz, AD9222-50 –30 1.0 0.8 –35 0.6 –40 0.2 CMRR (dB) INL (LSB) 0.4 0 –0.2 –45 –50 –55 –0.4 –60 –0.
PAGE 20
AD9222 Data Sheet 0 2.5 –1 0.3 LSB rms –3 AMPLITUDE (dBFS) NUMBER OF HITS (Millions) –3dB BANDWIDTH = 325MHz –2 2.0 1.5 1.0 –4 –5 –6 –7 –8 0.5 –9 N–2 N–1 N N+1 N+2 N+3 CODE Figure 51. Input-Referred Noise Histogram, AD9222-65 NPR = 60.3dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz –60 –80 –100 –120 5 10 15 20 FREQUENCY (MHz) 25 05967-041 AMPLITUDE (dBFS) –40 0 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 53. Full-Power Bandwidth vs.
PAGE 21
Data Sheet AD9222 THEORY OF OPERATION The AD9222 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic.
PAGE 22
AD9222 Data Sheet 90 90 SFDR (dBc) 85 85 80 80 SNR/SFDR (dB) 75 SNR (dB) 70 65 75 SNR (dB) 70 65 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) 60 0.2 05967-044 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 55. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, AD9222-50 05967-042 SNR/SFDR (dB) SFDR (dBc) Figure 57. SNR/SFDR vs.
PAGE 23
Data Sheet AD9222 For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core.
PAGE 24
AD9222 Data Sheet For optimum performance, the AD9222 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 63 shows a preferred method for clocking the AD9222. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer.
PAGE 25
Data Sheet AD9222 Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 69, the power dissipated by the AD9222 is proportional to its sample rate.
PAGE 26
AD9222 Data Sheet In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 4.
PAGE 27
Data Sheet AD9222 An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 73 and Figure 74. Figure 75 and Figure 76 show examples of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position.
PAGE 28
AD9222 Data Sheet 500 500 ULS: 7591/15591 400 300 EYE DIAGRAM VOLTAGE (mV) 200 100 0 –100 –200 –300 –0.5ns 0ns 0.5ns 1.0ns 100 0 –100 –200 –300 140 120 120 100 80 60 40 400 –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 100 80 60 40 20 –100ps 0ps 100ps 200ps 300ps 05967-105 –200ps 0 –200ps Figure 76. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65 EYE DIAGRAM VOLTAGE (mV) 200 –500 –1.5ns 1.
PAGE 29
Data Sheet AD9222 Two output clocks are provided to assist in capturing data from the AD9222. The DCO is used to clock the output data and is equal to six times the sample clock (CLK) rate. Data is clocked out of the AD9222 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. Table 9.
PAGE 30
AD9222 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility with lower and higher resolution systems.
PAGE 31
Data Sheet AD9222 CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the AVDD current of the ADC to a nominal 450 mA at 65 MSPS.
PAGE 32
AD9222 Data Sheet External Reference Operation 0.02 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 –0.14 –0.16 –0.18 –40 5 –20 0 20 40 60 TEMPERATURE (°C) 0 Figure 82. Typical VREF Drift, AD9222-50 –10 –15 –20 –25 05727-083 VREF ERROR (%) –5 –30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 81. VREF Accuracy vs. Load, AD9222-50 Rev. F | Page 32 of 60 80 05967-028 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference.
PAGE 33
Data Sheet AD9222 SERIAL PORT INTERFACE (SPI) The AD9222 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 34
AD9222 Data Sheet HARDWARE INTERFACE The pins described in Table 14 compose the physical interface between the user’s programming device and the serial port of the AD9222. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met.
PAGE 35
Data Sheet AD9222 tDS tS tHI tH tCLK tDH tLO CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 05967-068 SDIO DON’T CARE Figure 84. Serial Timing Details Table 15.
PAGE 36
AD9222 Data Sheet MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22).
PAGE 37
Data Sheet AD9222 Table 16. Memory Map Register Addr.
PAGE 38
AD9222 Data Sheet Addr. (Hex) 14 Parameter Name output_mode (MSB) Bit 7 X 15 output_adjust 16 Bit 5 X X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power, (IEEE 1596.
PAGE 39
Data Sheet AD9222 Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9222, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD.
PAGE 40
AD9222 Data Sheet EVALUATION BOARD individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed.
PAGE 41
Data Sheet AD9222 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 Ω resistors and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 μF capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation.
PAGE 42
AD9222 Data Sheet To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. • • • Remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. Remove L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 on the AD8334 analog outputs.
PAGE 43
Rev. F | Page 43 of 60 Channel A P101 Figure 90. Evaluation Board Schematic, DUT Analog Inputs VGA Input Connection R115 64.9Ω R114 0Ω−DNP INH2 R102 64.9Ω R101 0Ω−DNP DNP: DO NOT POPULATE. Ain P103 Channel B Ain INH1 Ain DNP P104 Ain 0Ω R117 R103 0Ω DNP P102 C109 0.1µF C108 0.1µF AVDD_DUT R116 0Ω FB104 10Ω E102 R125 1KΩ R126 1kΩ 1 R113 3 2 C114 0.1µF 0Ω−DNP R124 4 5 6 R118 0Ω−DNP C107 0.
PAGE 44
Rev. F | Page 44 of 60 Ain Figure 91. Evaluation Board Schematic, DUT Analog Inputs (Continued) P203 Channel F VGA Input Connection R218 64.9Ω R217 0Ω−DNP INH6 R202 64.9Ω R201 0Ω−DNP DNP: DO NOT POPULATE. Ain P201 Channel E INH5 Ain DNP P204 Ain DNP P202 R219 0Ω R203 0Ω C209 0.1µF C208 0.1µF AVDD_DUT R220 0Ω FB204 10Ω 1 R231 1kΩ 2 3 CM6 R232 1kΩ 1 CH_F CM6 CH_F 3 2 1 1 CM5 CH_E CM5 CH_E R211 1kΩ R212 1kΩ E202 E201 C202 0.1µF C201 0.
PAGE 45
Rev. F | Page 45 of 60 16 D+H D−H DRVDD DRGND VIN−D D+C VIN+D D−C D+D RBIAS D−D FCO+ FCO− DCO+ AVDD DCO− D+E VIN+E D−E VIN−E D+F AVDD VIN−F D+G D−F VIN+F D−G 30 28 29 27 26 25 24 22 23 21 20 18 CHB CHB CHD CHD FCO FCO Figure 92. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface CHC CHC C305 0.1µF VOUT AVDD 32 R308 470kΩ D−B 31 ADR510ARTZ TRIM/NC 1.0V D+B R310 10kΩ R309 4.
PAGE 46
Figure 93. Evaluation Board Schematic, Clock Circuitry Rev. F | Page 46 of 60 DNP: DO NOT POPULATE. 1 6 C411 0.1µF R418 0Ω 7 0Ω 9 S7 S6 HSMS-2812-TR1G CR401 S8 10 5 4 8 S9 11 2 3 VREF S5 S4 S1 S2 14 0Ω S10 15 R416 S9 S10 SIGNAL=DNC;27,28 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 S8 12 C403 0.1µF E401 GND_PAD AD9515BCPZ S7 T401 R417 0Ω 1 SYNCB CLKB S6 13 R405 0Ω R415 R413 10kΩ 5 3 CLK AVDD_3.3V S5 16 Enc OPT_CLK R407 0Ω R412 DNP DNP R411 49.
PAGE 47
1 CW C515 0.018µF L502 120nH GND VG12 Variable Gain Circuit (0−1.0V DC) External Variable Gain Drive Rev. F | Page 47 of 60 R508 274Ω INH1 C524 0.1µF 16 15 INH3 LMD3 VIN4 LOP4 VIP4 LON4 COM4X LMD1 LMD4 INH1 INH4 COM1 COM4 COM3 L501 120nH 0.1µF C513 27 26 25 24 23 19 18 VG12 VG34 External Variable Gain Drive Figure 94. Evaluation Board Schematic, Optional DUT Analog Input Drive VG34 AVDD_5V 22 R509 274Ω 17 C527 0.
PAGE 48
1 2 EXT VG JP601 CW GND VG56 EXT VG Variable Gain Circuit (0−1.0V DC) External Variable Gain Drive Rev. F | Page 48 of 60 R608 274Ω INH5 C624 0.1µF 16 15 INH3 LMD3 COM3X 30 61 LMD1 LMD4 INH1 INH4 62 COM1 L601 120nH 0.1µF C613 AVDD_5V 31 GAIN34 VPS4 26 27 VG78 VIN4 25 AVDD_5V LON4 LOP4 VIP4 24 23 COM4 20 19 18 17 GND VG78 VG56 External Variable Gain Drive Figure 95.
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OPTIONAL GREEN Rev. F | Page 49 of 60 GND Figure 96. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry ADP3339ZAKC−1.8-RL 1 GND DNP: DO NOT POPULATE. 2 2 OUT 4 OUT 4 2 J702 1 E701 0Ω−DNP R704 C717 1µF L706 10µH C715 1µF L705 10µH 0Ω−DNP DUT_DRVDD DUT_AVDD 0Ω−DNP R705 C721 1µF PWR_IN C719 1µF PWR_IN R714 10kΩ R715 10kΩ R711 10kΩ 3 SDI_CHA C716 1µF 10 IN IN U706 3 ADP3339ZAKC−3.
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Data Sheet 05967-079 AD9222 Figure 97. Evaluation Board Layout, Primary Side Rev.
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AD9222 05967-080 Data Sheet Figure 98. Evaluation Board Layout, Ground Plane Rev.
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Data Sheet 05967-081 AD9222 Figure 99. Evaluation Board Layout, Power Plane Rev.
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AD9222 05967-082 Data Sheet Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev.
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AD9222 Data Sheet Table 17. Evaluation Board Bill of Materials (BOM) 1 Item 1 2 Qnty.
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Data Sheet Item 8 Qnty. per Board 8 9 1 10 9 11 16 12 4 13 Reference Designator C503, C514, C520, C526, C603, C614, C620, C626 C704 AD9222 Device Capacitor Pkg. 402 Value 22 pF, ceramic, NPO, 5% tol, 50 V Mfg. Murata Mfg. Part Number GRM1555C1H220JZ01D Capacitor 1206 Rohm TCA1C106M8R Capacitor 603 Murata GRM188R61C105KA93D Capacitor 805 0.
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AD9222 Item 26 Qnty. per Board 32 27 1 28 9 29 Data Sheet Reference Designator L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 Device Resistor Pkg. 805 Value 0 Ω, 1/8 W, 5% tol Mfg. NIC Components Corp. Mfg. Part Number NRC04Z0TRF Oscillator SMT Clock oscillator, 50.00 MHz, 3.3 V, ±5% duty cycle Side-mount SMA for 0.
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Data Sheet Item 37 Qnty. per Board 8 38 3 Reference Designator R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 39 1 40 AD9222 Device Resistor Pkg. 402 Value 499 Ω, 1/16 W, 1% tol Resistor 402 100 kΩ, 1/16 W, 1% tol R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol 1 R404 Resistor 402 41 1 R309 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol 4.
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AD9222 Data Sheet Item 55 Qnty. per Board 9 56 2 Reference Designator T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 57 2 58 59 60 Device Transformer Pkg. CD542 IC SOT-223 U501, U601 IC CP-64-3 1 1 1 U706 U705 U301 IC IC IC SOT-223 SOT-223 CP-64-3 61 1 U302 IC SOT-23 62 1 U401 IC 63 1 U702 IC 64 1 U703 IC 65 1 U701 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value ADT1-1WT+, 1:1 impedance ratio transformer ADP33339AKC-1.8-RL, 1.5 A, 1.
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Data Sheet AD9222 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 0.22 MIN 7.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 02-23-2010-B 0.80 MAX 0.65 TYP 12° MAX 16 17 33 32 TOP VIEW 1.00 0.85 0.80 7.55 7.50 SQ 7.