Datasheet

Data Sheet AD9222
Rev. F | Page 3 of 60
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
AD9222-40
AD9222-50
AD9222-65
Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION
12
12
12
Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±1 ±8 ±1 ±8 ±1 ±8 mV
Offset Matching Full ±3 ±8 ±3 ±8 ±3 ±8 mV
Gain Error Full ±0.4 ±1.2 ±1.5 ±2.5 ±3.5 ±5 % FS
Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.4 ±0.8 % FS
Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 ±0.25 ±0.6 LSB
Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 ±0.4 ±1 LSB
TEMPERATURE DRIFT
Offset Error Full ±2 ±2 ±2 ppm/°C
Gain Error Full ±17 ±17 ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ±21 ±21 ppm/°C
REFERENCE
Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 ±2 ±30 mV
Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 3 mV
Input Resistance Full 6 6 6 kΩ
ANALOG INPUTS
Differential Input Voltage Range
(VREF = 1 V)
Full 2 2 2 V p-p
Common-Mode Voltage Full AVDD/2 AVDD/2 AVDD/2 V
Differential Input Capacitance
Full
7
7
7
pF
Analog Bandwidth, Full Power Full 325 325 325 MHz
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IAVDD Full 338 348.5 357.5 367.5 450 470 mA
IDRVDD Full 51 53.6 53.5 56.2 56.6 60.5 mA
Total Power Dissipation
(Including Output Drivers)
Full 700 722 740 760 910 950.5 mW
Power-Down Dissipation Full 2 11 2 11 2 11 mW
Standby Dissipation
2
Full 83 89 100 mW
CROSSTALK Full −90 −90 −90 dB
CROSSTALK (Overrange Condition)
3
Full −90 −90 −90 dB
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
This can be controlled via SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.