Datasheet

AD9230-11
Rev. 0 | Page 17 of 28
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230-11 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 24 shows a preferred method for clocking the AD9230-11.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9230-11 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230-11 and preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
CLOCK
INPUT
50Ω
100Ω
CLK–
CLK+
ADC
AD9230-11
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
07101-017
Figure 24. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple
a differential PECL signal to the sample clock input pins as
shown in Figure 25. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9230-11
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
07101-018
50Ω* 50Ω*
Figure 25. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50Ω* 50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9230-11
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
07101-019
Figure 26. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 F capacitor
in parallel with a 39 kΩ resistor (see Figure 27). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V (as shown in
Figure 28), making the selection of the drive logic voltage very
flexible.
0.1µF
0.1µF
0.1µF
39kΩ
CMOS DRIVER
50Ω*
OPTIONAL
100Ω
0.1µF
CLK
CLK
*50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9230-11
A
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
07101-020
Figure 27. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
CMOS DRIVER
CLK
CLK
*50Ω RESISTOR IS OPTIONAL.
0.1µF
CLK–
CLK+
A
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
ADC
AD9230-11
CLOCK
INPUT
50Ω*
OPTIONAL
100Ω
07101-021
Figure 28. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9230-11 contains a duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the perform-
ance of the AD9230-11. When the DCS is on, noise and distortion
performance are nearly flat for a wide range of duty cycles.
However, some applications may require the DCS function to
be off. If so, keep in mind that the dynamic range performance can
be affected when operated in this mode. See the Configuration
Using the SPI section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.