Datasheet

AD9230-11
Rev. 0 | Page 20 of 28
HARDWARE INTERFACE
Table 9. Serial Port Interface Pins
Mnemonic Function
SCLK
SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB
CSB (chip select bar) is an active low control that
gates the read and write cycles.
RESET
Master Device Reset. When asserted, device
assumes default settings. Active low.
The pins described in Table 9 comprise the physical interface
between the user’s programming device and the serial port
of the AD9230-11. All serial pins are inputs, which is an open-
drain output and should be tied to an external pull-up or
pull-down resistor (suggested value of 10 kΩ).
This interface is flexible enough to be controlled by either PROMS
or PIC microcontrollers as well. This provides the user with an
alternate method to program the ADC other than using an SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9230-11.
The falling edge of CSB, in conjunction with the rising edge of
the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 33
and Table 11.
CONFIGURATION WITHOUT THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins can alternately serve as
standalone CMOS-compatible control pins. When the device is
powered up, it is assumed that the user intends to use the pins
as static control lines for the duty cycle stabilizer. In this mode,
the CSB pin should be connected to AVDD, which disables the
serial port interface.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, at www.analog.com.
Table 10. Mode Selection
Mnemonic External Voltage Configuration
SDIO/DCS AVDD Duty cycle stabilizer enabled
AGND Duty cycle stabilizer disabled
SCLK/DFS AVDD Twos complement enabled
AGND Offset binary enabled
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
07101-027
Figure 33. Serial Port Interface Timing Diagram