Datasheet

AD9230-11
Rev. 0 | Page 7 of 28
TIMING DIAGRAMS
N – 1
N
N + 2
N + 3
N + 4
N + 5
N + 1
CLK+
N – 6 N – 5 N – 4 N – 3 N – 2
CLK–
DCO+
DCO–
Dx+
Dx–
VIN
t
A
t
CH
t
CL
1/ f
S
t
CPD
t
SKEW
t
PD
07101-002
Figure 2. Single Data Rate Mode
N – 1
N
N + 2
N + 3
N + 4
N + 5
N + 1
CLK+
CLK–
DCO+
DCO–
D5
N – 7
NO
DATA
D5
N – 6
NO
DATA
D5
N – 5
NO
DATA
D5
N – 4
NO
DATA
D5
N – 3
NO
DATA
D5+
D5–
D10
N – 7
D4
N – 6
D10
N – 6
D4
N – 5
D10
N – 5
D4
N – 4
D10
N – 4
D4
N – 3
D10
N – 3
D4
N – 2
D4/D10+
D4/D10–
VIN
t
A
t
CH
t
CL
1/ f
S
t
CPD
t
SKEW
t
PD
6 MSBs
5 LSBs
07101-003
Figure 3. Double Data Rate Mode