Datasheet

AD9253 Data Sheet
Rev. 0 | Page 10 of 40
10065-082
D0–x
D0+x
FCO–
DCO+
CLK+
VIN±x
CLK–
DCO–
FCO+
D10
N – 17
MSB
N–17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D1
N – 17
D0
N – 17
MSB
N – 16
D10
N – 16
t
A
t
DATA
t
EH
t
FCO
t
FRAME
t
PD
t
CPD
t
EL
N – 1
N
Figure 7. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode
S
YNC
CLK+
t
HSYNC
t
SSYNC
10065-079
Figure 8. SYNC Input Timing Requirements