Datasheet

AD9253 Data Sheet
Rev. 0 | Page 34 of 40
MEMORY MAP REGISTER TABLE
The AD9253 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high,
the SPI enters a soft reset, where all of the user registers revert
to their default values and Bit 2 is automatically cleared.
Table 17.
ADDR
(Hex) Parameter Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex) Comments
Chip Configuration Registers
0x00 SPI port
configuration
0 =
SDO
active
LSB first Soft
reset
1 =
16-bit
address
1 =
16-bit
address
Soft
reset
LSB first 0 = SDO
active
0x18 The nibbles
are mirrored
so that LSB-
first or MSB-
first mode
registers
correctly. The
default for
ADCs is 16-bit
mode.
0x01 Chip ID (global) 8-bit chip ID, Bits[7:0]
AD9253 0x8F = quad 14-bit 80 MSPS/105 MSPS/125 MSPS serial LVDS
0x8F Unique chip
ID used to
differentiate
devices; read
only.
0x02 Chip grade
(global)
Open Speed grade ID[6:4]
100 = 80 MSPS
101 = 105 MSPS
110 = 125 MSPS
Open Open Open Open Unique
speed grade
ID used to
differentiate
graded
devices; read
only.
Device Index and Transfer Registers
0x05 Device index Open Open Clock
Channel
DCO
Clock
Channel
FCO
Data
Channel
D
Data
Channel
C
Data
Channel
B
Data
Channel
A
0x3F Bits are set to
determine
which device
on chip
receives the
next write
command.
The default is
all devices on
chip.
0xFF Transfer Open Open Open Open Open Open Open Initiate
override
0x00 Set resolution/
sample rate
override.
Global ADC Function Registers
0x08 Power modes
(global)
Open Open External
power-
down
pin
function
0 = full
power-
down
1 =
standby
Open Open Open Power mode
00 = chip run
01 = full power-
down
10 = standby
11 = reset
0x00 Determines
various
generic
modes of chip
operation.
0x09 Clock (global) Open Open Open Open Open Open Open Duty
cycle
stabilize
0 = off
1 = on
0x01 Turns duty
cycle stabilizer
on or off.