Datasheet

AD9255 Data Sheet
Rev. C | Page 14 of 44
Pin No. Mnemonic Type Description
24
D10/11+
Output
LVDS Output Data Bit 10/Bit 11—True.
23 D10/11− Output LVDS Output Data Bit 10/Bit 11—Complement.
26 D12/13+ (MSB) Output LVDS Output Data Bit 12/Bit 13—True.
25 D12/13− (MSB) Output LVDS Output Data Bit 12/Bit 13—Complement.
28 OR+ Output LVDS Overrange Output—True.
27 OR− Output LVDS Overrange Output—Complement.
8 DCO+ Output LVDS Data Clock Output—True.
7 DCO− Output LVDS Data Clock Output—Complement.
SPI Control
31 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
30 SDIO/DCS Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
32 CSB Input SPI Chip Select (Active Low).
ADC Configuration
6 OEB Input Output Enable Input (Active Low).
35
DITHER
Input
In external pin mode, this pin sets dither to on (active high). Pull low for control via SPI
in the SPI mode.
41 LVDS_RS Input
In external pin mode, this pin sets LVDS reduced swing output mode (active high). Pull
low for control via SPI in the SPI mode.
44 LVDS Input
In external pin mode, this pin sets LVDS output mode (active high). Pull low for control
via SPI in the SPI mode.
48 PDWN Input
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as
power-down or standby.