Datasheet

AD9255 Data Sheet
Rev. C | Page 6 of 44
Parameter
1
Temp
AD9255BCPZ-80
2
AD9255BCPZ-105
2
AD9255BCPZ-125
2
Unit
Min Typ Max Min Typ Max Min Typ Max
WORST OTHER (HARMONIC OR SPUR)
Without Dither
f
IN
= 2.4 MHz 25°C −106 −105 −101
dBc
f
IN
= 70 MHz 25°C −106 −104 −104
dBc
Full
−94 −95
−91
dBc
f
IN
= 140 MHz 25°C −104 −104 −103
dBc
f
IN
= 200 MHz 25°C −102 −103 −100
dBc
With On-Chip Dither
f
IN
= 2.4 MHz 25°C −105 −106 −101
dBc
f
IN
= 70 MHz 25°C −106 −105 −104
dBc
Full
−97 −99
−98
dBc
f
IN
= 140 MHz 25°C −103 −103 −103
dBc
f
IN
= 200 MHz 25°C −100 −101 −100
dBc
TWO-TONE SFDR
Without Dither
f
IN
= 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C
93 90
95
dBc
f
IN
= 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C
80 78
79
dBc
ANALOG INPUT BANDWIDTH 25°C
650 650
650
MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
The suffix following the part number refers to the model found in the Ordering Guide section.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS dierential input, 1.0 V internal reference, and DCS
enabled, unless otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Capacitance Full 4 pF
Input Resistance Full 8 10 12 kΩ
SYNC INPUT
Logic Compliance CMOS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Capacitance Full 1 pF
Input Resistance Full 12 16 20 kΩ
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