Datasheet

Data Sheet AD9257
Rev. A | Page 25 of 40
Two output clocks are provided to assist in capturing data from
the AD9257. The DCO is used to clock the output data and is
equal to 7× the sample clock (CLK) rate for the default mode of
operation. Data is clocked out of the AD9257 and must be captured
on the rising and falling edges of the DCO that supports double
data rate (DDR) capturing. The FCO is used to signal the start
of a new output byte and is equal to the sample clock rate (see
the Timing Diagrams section).
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 180° relative to the
output data edge.
A 12-bit serial stream can also be initiated from the SPI. This
allows the user to implement and test compatibility to lower
resolution systems. When changing the resolution to a 12-bit
serial stream, the data stream is shortened. See Figure 3 for the
12-bit example.
In default mode, as shown in Figure 2, the MSB is first in the
data output serial stream. This can be inverted so that the LSB is
first in the data output serial stream by using the SPI.
There are 12 digital output test pattern options available that can
be initiated through the SPI. This is a useful feature when validating
receiver capture and timing (see Table 11 for the output bit
sequencing options that are available). Some test patterns have
two serial sequential words and can be alternated in various ways,
depending on the test pattern chosen. Note that some patterns
do not adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in Register 0x19,
Register 0x1A, Register 0x1B, and Register 0x1C.
Table 11. Flexible Output Test Modes
Output Test
Mode Bit
Sequence
Pattern Name Digital Output Word 1 Digital Output Word 2
Subjec
t to
Data
Format
Select
Notes
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
N/A Yes Offset binary code shown
0010 +Full-scale short 1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
N/A Yes Offset binary code shown
0011 −Full-scale short 0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
N/A Yes Offset binary code shown
0100 Checkerboard 1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
No
0101 PN sequence long
1
N/A N/A Yes PN23
ITU 0.150
X
23
+ X
18
+ 1
0110 PN sequence short
1
N/A N/A Yes PN9
ITU O.150
X
9
+ X
5
+ 1
0111 One-/zero-word
toggle
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A No
1010 1× sync 0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
N/A No
1011 One bit high 1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
N/A No Pattern associated with
the external pin
1100 Mixed frequency 1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
N/A No
1
All test mode options except PN sequence short and PN sequence long can support 12-bit to 14-bit word lengths to verify data capture to the receiver.