Datasheet

Data Sheet AD9257
Rev. A | Page 7 of 40
Timing Diagrams
DCO–
DCO+
D– x
D+ x
FCO–
FCO+
VIN± x
CLK–
CLK+
MSB
N – 17
D12
N – 17
D11
N – 17
D10
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D0
N – 17
D1
N – 17
D12
N – 16
MSB
N – 16
N – 1
t
A
t
EH
t
CPD
t
FCO
t
PD
t
DATA
t
FRAME
t
EL
N
10206-002
Figure 2. Word-Wise DDR,1× Frame, 14-Bit Output Mode (Default)
DCO–
DCO+
D– x
D+ x
FCO–
FCO+
VIN± x
CLK–
CLK+
MSB
N – 17
D10
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D1
N – 17
D0
N – 17
D10
N – 16
MSB
N – 16
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
A
t
EL
10206-003
Figure 3. Word-Wise DDR, 1× Frame, 12-Bit Output Mode
SYNC
CLK+
t
HSYNC
t
SSYNC
10206-004
Figure 4. SYNC Input Timing Requirements