Datasheet
UG-191 Evaluation Board User Guide
Rev. 0 | Page 10 of 24
09346-014
SHARE PADS
REF IN CKT
DEFAULT LOW -> CLKB DISABLED
CONNECT -> CLKB ENABLED
D3B/(D1A+/D1B+)
D2B/(D1A-/D1B-)
D1B/(D0A+/D0B+)
D0B/(D0A-/D0B-)
AVDD
DEFAULT LOW -> OUTPUT ENABLED
D4A/(D6A-/D6B-)
D3A/(D5A+/D5B+)
AD9286
65/135/250 MSPS
OUTPUT_ENABLE
SPI_SCLK/CMOS_LVDS
SPI_SDIO/PWRDN
40
D5A/(D6A+/D6B+)
D2A/(D5A-/D5B-)
D1A/(D4A+/D4B+)
D0A/(D4A-/D4B-)
DCOA/(DCO+)
DCOB/(DCO-)
D7B/(D3A+/D3B+)
D6B/(D3A-/D3B-)
D5B/(D2A+/D2B+)
D4B/(D2A-/D2B-)
2
AIN A+
AIN B-
AIN B+
AVDD
REF IN
AVDD
CMV OUT
AVDD
AVDD
13
AVDD
ENC B+
14
DRVDD
DRGND
CLOCK B ENABLE
RBIAS
ENC B-
35
ENC A-
AVDD
48
1
AVDD
1-2 SPI MODE (SCLK)
2-3 LVDS MODE
NO CONNECT CMOS MODE (DEFAULT)
44
AVDD
DECOUPLING CAPACITORS, ONE ON THE TOP AND ONE ON THE BOTTOM CLOSE TO THE PINS
AVDD PIN 1
AVDD
PAD
12
31
AVDD PINS 8 & 9
AVDD PIN 4
DRVDD PIN 39 1-2 SPI MODE (SDIO)
2-3 PWRDN MODE
NO CONNECT (DEFAULT)
D7A(D7A+/D7B+)
36
D6A(D7A-/D7B-)
DRGND
8
24
15
6
37
38
3941
2220
18
16
47
46
45 43
42
34
33
32
30
29
28
27
26
25
23211917
11
10
7
5
4
AVDD PINS 45
AVDD PINS 16
AVDD PINS 13
AVDD PINS 12
AVDD PIN 6
DRVDD PIN 20
ENC A+
SPI_CSB
DUT
AIN A-
9
AVDD PINS 48
3
DRVDD
AVDD
DNI
0
R203
R202
R206
DNI
C225
2
0.1UF
ADR512ARTZ-REEL7
DNI
1
2.7K
DNI
TSW-102-08-G-S
J204
43
AVDD
AIN-
ENC_A+
ENC_A-
CSB_DUT
SDIO_DUT_PWRDN
SCLK_DUT_CMOS_LVDS
TSW-102-08-G-S
1
DRVDD
D4B_D2M
D5B_D2P
D6B_D3M
D7B_D3P
D0A_D4M
D1A_D4P
D2A_D5M
D3A_D5P
D4A_D6M
D5A_D6P
J203
DNI
1
2
27
26
DRVDD
ENC_B-
ENC_B+
1
3
U202
R1
C227
C226
PAD
9
8
7
6
5
48
47
46
45
44
42
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
U201
3
2
1
J202
3
2
1
J201
3
2
R204
C224
C221 C222
C219 C220
C218
C216
C214
C212
C210
C208
C206
C202
C204
C223
C215
C211
C209
C201
1
TP201
R205
R201
2
RBIAS
SG-MLF-7006
AVDD
D2B_D1M
D1B_D0P
D0B_D0M
SAMTECTSW10608GS3PIN
DRVDD
DNI
SCLK_DUT
SCLK_DUT_CMOS_LVDS
0
AVDD
AVDD
AVDD
AVDD
AVDD
.1UF
DNI
.1UF
AVDD
AVDD
AVDD
AVDD
DRVDD
AVDD
DRVDD DRVDD
DRVDD
10K
DRVDD
DCO_B
D6A_D7M
GND
.1UF
.1UF
.1UF .1UF
.1UF .1UF
.1UF
.1UF
.1UF
SDIO_DUT_PWRDN
.1UF
DNI
DNI
DNI
DNI
.1UF
AVDD
AVDD
.1UF
D3B_D1P
GND
SAMTECTSW10608GS3PIN
SDIO_DUT
.1UF
.1UF
DNI
.1UF
D7A_D7P
CMV_OUT
AVDD
DCO_A
0.1UF
BLK
DNI
DNI
10K
5K
0
DNI
GND
DNI
0.1UF
AVDD
AVDD
AIN+
AVDD
DNI
0.1UF
0
DNI
0.1UF
DNI
REF_AVDD
TRIM
V_N
V_P
CW
Figure 14. DUT and Related Circuit