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Quad, 8-Bit, 100 MSPS,

Serial LVDS 1.8 V ADC

Data Sheet

AD9287

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

4 ADCs integrated into 1 package

133 mW ADC power per channel at 100 MSPS

SNR = 49 dB (to Nyquist)

ENOB = 7.85 bits

SFDR = 65 dBc (to Nyquist)

Excellent linearity

DNL = ±0.2 LSB (typical)

INL = ±0.2 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

295 MHz full-power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

Test equipment

GENERAL DESCRIPTION

The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con-

verter (ADC) with an on-chip sample-and-hold circuit designed

for low cost, low power, small size, and ease of use. The product

operates at a conversion rate of up to 100 MSPS and is optimized

for outstanding dynamic performance and low power in

applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock output (DCO) for

FUNCTIONAL BLOCK DIAGRAM

SERIAL

LVDS

REF

SELECT

–

AD9287

AGND

VIN – A

VIN + A

VIN – B

VIN + B

VIN – D

VIN + D

VIN – C

VIN + C

SENSE

VREF

DRVDD

REFT

REFB

D – A

D + A

D – B

D + B

D – D

D + D

D – C

D + C

FCO–

FCO+

DCO+

DCO–

CLK+

DRGND

CLK–

SERIAL PORT

INTERFACE

CSB

SCLK/DTP

SDIO/ODMRBIAS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

DATA RATE

MULTIPLIER

0.5V

05966-001

T/H

Figure 1.

capturing data on the output and a frame clock output (FCO)

for signaling a new output byte are provided. Individual-channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

The AD9287 is available in an RoHS compliant, 48-lead LFCSP. It is

specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Four ADCs are contained in a small, space-

saving package.

2. Low power of 133 mW/channel at 100 MSPS.

3. Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 400 MHz and supports

double data rate (DDR) operation.

4. User Flexibility. The SPI control offers a wide range of flexible

features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9219 (10-bit),

AD9228 (12-bit), and AD9259 (14-bit).

Summary of content (52 pages)

PAGE 1
Quad, 8-Bit, 100 MSPS, Serial LVDS 1.8 V ADC AD9287 Data Sheet 4 ADCs integrated into 1 package 133 mW ADC power per channel at 100 MSPS SNR = 49 dB (to Nyquist) ENOB = 7.85 bits SFDR = 65 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.2 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 295 MHz full-power analog bandwidth 2 V p-p input voltage range 1.
PAGE 2
AD9287 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 21 General Description .........................................................................
PAGE 3
Data Sheet AD9287 REVISION HISTORY 12/11—Rev. D to Rev. E Changes to Output Signals Section and Figure 60......................35 Change to Default Operation and Jumper Selection Settings Section ..............................................................................................36 Changes to Figure 63 ......................................................................39 Added Endnote 2 in Ordering Guide ...........................................51 4/10—Rev. C to Rev. D Changes to Table 16 .
PAGE 4
AD9287 Data Sheet SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation at 1.
PAGE 5
Data Sheet AD9287 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 49.7 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 49.7 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 49.7 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 49.
PAGE 6
AD9287 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3.
PAGE 7
Data Sheet AD9287 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4.
PAGE 8
AD9287 Data Sheet TIMING DIAGRAMS N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x MSB N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D6 N–8 D5 N–8 D4 N–8 D3 N–8 D2 N–8 D1 N–8 05966-040 D+x Figure 2. 8-Bit Data Serial Stream, MSB First (Default) N–1 VIN ± x tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D+x Figure 3.
PAGE 9
Data Sheet AD9287 N–1 VIN ± x tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x D0 N–9 D1 N–9 D2 N–9 D3 N–9 D4 N–9 D5 N–9 D6 N–9 LSB N–8 D0 N–8 D1 N–8 D2 N–8 D3 N–8 D4 N–8 05966-041 LSB N–9 D+x Figure 4. 8-Bit Data Serial Stream, LSB First Rev.
PAGE 10
AD9287 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− VIN + x, VIN − x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To Rating AGND DRGND DRGND DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.
PAGE 11
Data Sheet AD9287 VIN + C AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD VIN + B VIN – B 46 45 44 43 42 41 40 39 38 37 VIN – C 48 47 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AVDD 1 AVDD 35 AVDD 34 VIN – A 33 VIN + A AVDD 5 32 AVDD AVDD 6 AD9287 31 PDWN CLK– 7 TOP VIEW (Not to Scale) 30 CSB CLK+ 8 29 SDIO/ODM AVDD 9 28 SCLK/DTP AVDD 10 27 AVDD DRGND 11 26 DRGND DRVDD 12 25 DRVDD VIN – D 3 DCO+ 24 23 DCO– 21 FCO– FCO+ 22 D + A 20
PAGE 12
AD9287 Pin No. 34 37 38 40 41 42 43 44 47 48 Data Sheet Mnemonic VIN − A VIN − B VIN + B RBIAS SENSE VREF REFB REFT VIN + C VIN − C Description ADC A Analog Input Complement ADC B Analog Input Complement ADC B Analog Input True External resistor sets the internal ADC core bias current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC C Analog Input True ADC C Analog Input Complement Rev.
PAGE 13
Data Sheet AD9287 EQUIVALENT CIRCUITS DRVDD V V D– VIN ± x D+ DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit CLK+ V 05966-005 05966-030 V 10Ω 10kΩ 1.25V 10kΩ SCLK/DTP AND PDWN 10Ω 1kΩ 30kΩ 05966-033 05966-032 CLK– Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit RBIAS 30kΩ 05966-031 350Ω 05966-035 SDIO/ODM 100Ω Figure 11. Equivalent RBIAS Circuit Figure 8.
PAGE 14
AD9287 Data Sheet AVDD 70kΩ CSB 1kΩ 6kΩ Figure 14. Equivalent VREF Circuit Figure 12. Equivalent CSB Input Circuit 1kΩ 05966-036 SENSE 05966-037 05966-034 VREF Figure 13. Equivalent SENSE Circuit Rev.
PAGE 15
Data Sheet AD9287 TYPICAL PERFORMANCE CHARACTERISTICS AIN = –0.5dBFS SNR = 49.21dB ENOB = 7.88 BITS SFDR = 70.89dBc –10 –30 AMPLITUDE (dBFS) –50 –70 –90 –70 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) –110 05966-055 0 Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 100 MSPS 0 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) Figure 18. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 100 MSPS AIN = –0.5dBFS SNR = 49.17dB ENOB = 7.87 BITS SFDR = 62.
PAGE 16
AD9287 Data Sheet 80 80 75 70 70 60 2V p-p, SFDR SNR/SFDR (dB) SNR/SFDR (dB) 2V p-p, SFDR 65 60 55 50 40 30 60dB REFERENCE 50 20 2V p-p, SNR 2V p-p, SNR 45 30 40 50 60 70 80 90 100 fSAMPLE (MSPS) 0 –60 Figure 21. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 100 MSPS –50 –40 –30 –20 –10 0 ANALOG INPUT LEVEL (dBFS) 05966-058 20 05966-061 40 10 10 Figure 24. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 100 MSPS 80 AIN1 AND AIN2 = –7dBFS SFDR = 72.
PAGE 17
Data Sheet AD9287 80 0.5 75 0.4 0.3 60 0.1 DNL (LSB) 0.2 55 2V p-p, SNR (dB) 50 0 –0.1 45 –0.2 40 –0.3 35 –0.4 30 –0.5 10 1 100 1000 ANALOG INPUT FREQUENCY (MHz) 0 50 100 150 200 250 CODE Figure 27. SNR/SFDR vs. Analog Input Frequency, fSAMPLE = 100 MSPS 05966-066 2V p-p, SFDR (dBc) 65 05966-063 SNR/SFDR (dB) 70 Figure 30. DNL, fIN = 2.4 MHz, fSAMPLE = 100 MSPS –45.0 80 75 –45.5 65 –46.0 2V p-p, SFDR CMRR (dB) SINAD/SFDR (dB) 70 60 55 –46.5 –47.
PAGE 18
AD9287 Data Sheet 0 NPR = 40.12dB NOTCH = 18MHz NOTCH WIDTH = 3MHz –1 –50 –70 –90 –2 –3dB CUTOFF = 295MHz –3 –4 –5 –6 –7 –8 –9 –110 0 5 10 15 20 25 30 35 40 45 FREQUENCY (MHz) 50 05966-054 AMPLITUDE (dB) –30 05966-077 FUNDAMENTAL LEVEL (dBFS) –10 Figure 33. Noise Power Ratio (NPR), fSAMPLE = 100 MSPS –10 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 34. Full-Power Bandwidth vs. Frequency, fSAMPLE = 100 MSPS Rev.
PAGE 19
Data Sheet AD9287 THEORY OF OPERATION The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9287 is a differential switchedcapacitor circuit designed for processing differential input signals. The circuit can support a wide common-mode range while maintaining excellent performance.
PAGE 20
AD9287 Data Sheet ADT1-1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core.
PAGE 21
Data Sheet AD9287 0.1µF CLK+ CLK 50Ω1 Figure 42 shows a preferred method for clocking the AD9287. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9287 to approximately 0.8 V p-p differential.
PAGE 22
AD9287 Data Sheet Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 48, the power dissipated by the AD9287 is proportional to its sample rate.
PAGE 23
Data Sheet AD9287 placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that each trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 49.
PAGE 24
AD9287 Data Sheet EYE: ALL BITS ULS: 10000/15600 EYE: ALL BITS 400 EYE DIAGRAM VOLTAGE (V) EYE DIAGRAM VOLTAGE (V) 500 0 ULS: 9599/15599 200 0 –200 –400 –500 –1.0ns –0.5ns 0ns 0.5ns –1.0ns 1.0ns –0.5ns 0ns 0.5ns 1.0ns 50 0 –100ps 0ps 100ps 0 –150ps Figure 50.
PAGE 25
Data Sheet AD9287 Two output clocks are provided to assist in capturing data from the AD9287. The DCO is used to clock the output data and is equal to four times the sample clock (CLK) rate. Data is clocked out of the AD9287 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. Table 9.
PAGE 26
AD9287 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. A 10-, 12-, or 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility with higher resolution systems.
PAGE 27
Data Sheet AD9287 SCLK/DTP Pin RBIAS Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device powerup. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern.
PAGE 28
AD9287 Data Sheet Internal Reference Operation External Reference Operation A comparator within the AD9287 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 53), setting VREF to 1 V. The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics.
PAGE 29
Data Sheet AD9287 SERIAL PORT INTERFACE (SPI) The AD9287 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 30
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 Data Sheet If the user chooses not to use the SPI, these dual-function pins serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pin-strappable functions are supported on the SPI pins.
PAGE 31
Data Sheet AD9287 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22).
PAGE 32
AD9287 Data Sheet Table 16. Memory Map Register Addr.
PAGE 33
Data Sheet AD9287 Addr. (Hex) 14 Register Name output_mode (MSB) Bit 7 X 15 output_adjust 16 Bit 5 X X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power (IEEE 1596.
PAGE 34
AD9287 Data Sheet Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9287, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD.
PAGE 35
Data Sheet AD9287 EVALUATION BOARD board individually. Use P501 to connect a different supply for each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed.
PAGE 36
AD9287 Data Sheet DEFAULT OPERATION AND JUMPER SELECTION SETTINGS A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Populate R225 and R227 with 0 Ω resistors and remove R217 and R218 to disconnect the default clock path inputs. In addition, populate C207 and C208 with a 0.1 μF capacitor and remove C210 and C211 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation.
PAGE 37
Data Sheet AD9287 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. For more details on the AD8332 dual VGA, including how it works and its optional pin settings, consult the AD8332 data sheet.
PAGE 38
AD9287 Data Sheet AVDD_DUT R105 DNP R152 DNP CH_A R104 0Ω P102 VGA INPUT CONNECTION DNP INH1 AIN CHANNEL A R101 P101 DNP AIN FB102 R108 10Ω 33Ω T101 1 6 R106 DNP CM1 R103 0Ω R102 64.9Ω C101 0.1µF 2 5 3 4 CM1 VIN_A R161 499Ω C103 DNP C104 2.2pF R109 1kΩ FB103 R110 33Ω 10Ω C105 DNP R156 DNP R107 DNP R113 FB101 DNP 10Ω C102 0.1µF CH_A CM1 VIN_A E101 AVDD_DUT R111 1kΩ R112 1kΩ C106 DNP C107 0.
PAGE 39
P201 ENCODE INPUT ENC DNP P203 CLOCK CIRCUIT ENC AVDD AVDD VIN – D VIN + D AVDD AVDD CLK– CLK+ AVDD AVDD DRGND DRVDD VIN_C VIN_C AD9287 LFCSP CHC CHC CHB C224 0.1µF R216 0Ω R201 10kΩ AVDD AVDD VIN – A VIN + A AVDD PDWN C216 0.1µF R218 0Ω R217 0Ω OPT_CLK OPT_CLK 5 6 2 1 R221 10kΩ 1 1 U202 2 J203 2 J202 J201 DNP R231 DNP 1 CR201 HSMS2812 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 DNP: DO NOT POPULATE C213 0.1µF R233 DNP C214 1µF R232 DNP VREF_DUT 3 3 R237 0Ω 23 C211 0.
PAGE 40
CH_C R311 10kΩ DNP AVDD_5V C310 0.1µF 19 18 17 VOL2 VOH2 COMM 20 INH2 VPS2 LON2 RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 16 15 14 13 12 11 10 9 C321 0.1µF R314 10kΩ DNP VG C313 0.1µF C314 0.1µF 6 7 8 LMD1 LMD2 4 5 C309 1000pF R310 187Ω R317 274Ω C325 0.1µF C326 10µF R318 10kΩ C322 0.018µF C318 22pF C323 22pF L309 120nH INH4 L310 120nH C324 0.1µF INH3 Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit Rev.
PAGE 41
R414 10kΩ R412 10kΩ DNP HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V AVDD_5V OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL A AND CHANNEL B C413 10µF C410 0.1µF C409 0.1µF POWER DOWN ENABLE (0V TO 1V = DISABLE POWER) C414 0.1µF R411 10kΩ 25 26 27 28 29 30 31 32 CH_B C415 0.018µF R415 274Ω ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 U401 R407 187Ω C405 0.1µF R408 187Ω R405 374Ω 24 23 Figure 65.
PAGE 42
1 3 2 + C501 10µF 3.3V_AVDD DUT_DRVDD P4 4 P5 5 P6 6 P7 7 3 INPUT L501 10µH L508 10µH L502 10µH L503 10µH OUTPUT4 2 OUTPUT1 4 OUTPUT4 4 2 2 FER501 L505 10µH C513 1µF L504 10µH +3.3V AVDD_3.3V DUT_DRVDD DUT_AVDD C507 0.1µF C534 1µF PWR_IN C532 1µF PWR_IN 3 3 C517 0.1µF C525 0.1µF C527 0.1µF C519 0.1µF INPUT 2 OUTPUT4 4 OUTPUT1 ADP3339AKC-5 INPUT 2 OUTPUT4 4 OUTPUT1 ADP3339AKC-3.3 U502 C516 0.1µF C524 0.1µF C526 0.1µF C518 0.
PAGE 43
AD9287 05966-020 Data Sheet Figure 67. Evaluation Board Layout, Primary Side Rev.
PAGE 44
Data Sheet 05966-021 AD9287 Figure 68. Evaluation Board Layout, Ground Plane Rev.
PAGE 45
AD9287 05966-022 Data Sheet Figure 69. Evaluation Board Layout, Power Plane Rev.
PAGE 46
Data Sheet 05966-023 AD9287 Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev.
PAGE 47
Data Sheet AD9287 Table 17.
PAGE 48
AD9287 Data Sheet Value 6.0 V, 2.2 A tripcurrent resettable fuse 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz 10 Ω, test freq 100 MHz, 25% tol, 500 mA Manufacturer Tyco/Raychem Manufacturer’s Part Number NANOSMDC110F-2 Murata DLW5BSN191SQ2L Murata BLM18BA100SN1B 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header male, 4 × 3 triple row straight 100 mil header, male, 2 × 5 double row straight 10 μH, bead core 3.2 × 2.5 × 1.
PAGE 49
Data Sheet Item 35 Qty.
PAGE 50
AD9287 Data Sheet Item 57 Qty. 2 Reference Designator U301, U401 Device IC Package LFCSP, CP-32 58 59 60 1 1 1 U504 U502 U201 IC IC IC SOT-223 SOT-223 LFCSP, CP-48-1 61 1 U203 IC SOT-23 62 1 U202 IC 63 1 U403 IC 64 1 U404 IC 65 1 U402 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value AD8332ACP, ultralow noise precision dual VGA ADP3339AKC-5 ADP3339AKC-3.3 AD9287BCPZ-100, quad, 8-bit, 100 MSPS serial LVDS 1.8 V ADC ADR510ARTZ, 1.
PAGE 51
Data Sheet AD9287 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 48 0.50 REF 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 13 12 0.22 MIN 5.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5.50 SQ 5.45 (BOTTOM VIEW) 0.50 0.40 0.30 PIN 1 INDICATOR *5.55 EXPOSED PAD 25 24 TOP VIEW 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.